LTC3388-3 Linear Technology, LTC3388-3 Datasheet
LTC3388-3
Related parts for LTC3388-3
LTC3388-3 Summary of contents
Page 1
... Output voltages of 1.2V, 1.5V, 1.8V, 2.5V (LTC3388-1) and 2.8V, 3.0V, 3.3V, 5.0V (LTC3388-3) are pin selectable. The LTC3388-1/LTC3388-3 can operate with V the no load quiescent current remains below 1μA. L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks of Linear Technology Corporation ...
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... DataSheet.in LTC3388-1/LTC3388-3 ABSOLUTE MAXIMUM RATINGS V ............................................................. –0.3V to 22V IN D0, D1 ..............–0.3V to [Lesser of (V CAP ......................[Higher of –0. ......... –0.3V to [Lesser of (V IN2 OUT EN, STBY ..................................................... –0. PGOOD......................................................... –0. PIN CONFIGURATION TOP VIEW EN 1 STBY 2 CAP PACKAGE 10-LEAD (3mm 3mm) PLASTIC DFN = 125° ...
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... I V Quiescent Current When Disabled Q, Undervoltage Lockout Threshold UVLO IN V Regulated Output Voltage (LTC3388-1) OUT V Regulated Output Voltage (LTC3388-3) OUT PGOOD Threshold V PGOOD Output Low Voltage OL, PGOOD I Output Quiescent Current VOUT I PMOS Switch Peak Current PEAK I Available Output Current OUT ...
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... Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3388-1/LTC3388-3 are tested under pulsed load conditions such that T ≈ The LTC3388E-1/LTC3388E-3 are guaranteed to meet ...
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... Output vs Temperature (LTC3388-1) 1.54 SLEEP THRESHOLD 1.52 1.50 WAKE-UP THRESHOLD 1.48 1.46 1.44 1.42 1.40 PGOOD FALLING 1.38 1.36 1. 100 125 –50 – TEMPERATURE (°C) 338813 G08 2.8V Output vs Temperature (LTC3388-3) 2.90 2.85 SLEEP THRESHOLD 2.80 WAKE-UP THRESHOLD 2.75 2.70 2.65 PGOOD FALLING 2.60 2.55 2.50 75 100 125 –50 – TEMPERATURE (°C) 338813 G11 NMOS PMOS 105 125 ...
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... TEMPERATURE (°C) 338813 G14 V Line Regulation OUT (LTC3388-1) 1. 22μ 30mA 100μF , LOAD 1.54 1.52 1.50 1.48 1.46 1.44 1m 10m 338813 G17 I vs Temperature (LTC3388-3) VOUT 160 V = 5.0V OUT V = 3.3V OUT 140 V = 3.0V OUT V = 2.8V OUT 120 100 100 125 –50 – TEMPERATURE (° ...
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... V (V) IN 338813 G24 for V = 1.8V, IN OUT = 50mA = 100μA = 50μA = 30μA = 10μ (V) IN 338813 G26 LTC3388-1/LTC3388-3 Efficiency 100μH LOAD (LTC3388-1) 100 2.5V OUT 1.8V OUT V = 1.5V 10 OUT V = 1.2V ...
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... V = 3.3V 75 OUT V = 3.0V OUT V = 2.8V OUT (V) IN 338813 G31 Efficiency vs V for V = 3.3V, IN OUT L = 100μH (LTC3388-3) 100 50mA LOAD 100μA LOAD I = 50μA LOAD 30μA LOAD I = 10μA LOAD ...
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... GND (Exposed Pad Pin 11): Ground. The exposed pad should be connected to a continuous ground plane on the second layer of the printed circuit board by several vias directly under the LTC3388-1/LTC3388-3. LTC3388-1/LTC3388-3 (Pin 6): Sense pin used to monitor the output volt- (Pin 7): Internal low voltage rail to serve as gate drive to GND ...
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... DataSheet.in LTC3388-1/LTC3388-3 BLOCK DIAGRAM STBY INTERNAL RAIL GENERATION V IN2 40nA UVLO 1 V IN2 BUCK CONTROL 40nA 2 SLEEP BANDGAP REFERENCE 2 3 CAP IN2 GND OUT 10 PGOOD PGOOD – + REF 338813 BD 338813f ...
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... NMOS body diode. The LTC3388-1/ LTC3388-3 keeps the NMOS switch on during this time to prevent the conduction loss that would occur in the diode if the NMOS were off. If the PMOS is on when the sleep ...
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... LTC3388-1/LTC3388-3 OPERATION Four selectable voltages are available by tying the output select bits, D0 and D1, to GND or V four D0/D1 codes and their corresponding output voltages as well as the difference in output voltages between the LTC3388-1 and LTC3388-3. Table 1. LTC3388-1/LTC3388-3 Output Voltage Selection OUT ...
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... OPERATION Enable and Standby Modes Two logic pins, EN and STBY, determine the operating mode of the LTC3388-1/LTC3388-3. When EN is high and STBY is low the synchronous buck converter is enabled and will regulate the output if the input voltage is above the programmed output voltage and above the UVLO threshold ...
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... The sleep time decreases as the load current increases and/or as the output capacitor decreases. The DC sleep hysteresis window, V the programmed output voltage on the LTC3388-1 and LTC3388-3 respectively. Ideally this means that the sleep time is determined by the following equation: t SLEEP This is true for output capacitors on the order of 100μF or larger, but as the output capacitor decreases towards 10μ ...
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... Trade-offs between price, size, and DCR should be evaluated. Table 2 lists several inductors that work well with the LTC3388-1/LTC3388-3. I −I ) LOAD BUCK Table 2. Recommended Inductors for LTC3388-1/LTC3388-3 t LOAD when PGOOD goes high INDUCTOR TYPE OUT . I is the OUT ...
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... I will dominate this loss term which Q(SLEEP) is why the extremely low quiescent current in sleep of the LTC3388-1/LTC3388-3 is critical Internal MOSFET gate charge currents result from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched ...
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... The output capacitor should be sized to minimize the decline. reaches regulation, OUT The EN pin can be used to activate the LTC3388-1/LTC3388-3. For instance, in Figure 8 the LTC3388-1 is enabled by the PGOOD output of the LTC3588-1, a piezoelectric energy harvesting power supply, to create a 1.2V rail. The quies- ...
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... DataSheet.in LTC3388-1/LTC3388-3 PACKAGE DESCRIPTION 3.55 0.05 2.15 0. Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699 Rev C) 0.70 0.05 1.65 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.38 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 0.10 (4 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF 0.75 0.05 0.00 – 0.05 NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). ...
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... Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. LTC3388-1/LTC3388-3 BOTTOM VIEW OF EXPOSED PAD OPTION 1 ...
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... IN2 6V 2.2μF 10V GND * EXPOSED PAD MUST BE ELECTRICALLY ISOLATED FROM SYSTEM GROUND AND CONNECTED TO THE –3.3V RAIL ● www.linear.com V IN 1μF PGOOD 6V LTC3388-3 CAP 22μ IN2 V EN OUT D1 4.7μF D0 STBY 6V GND COMMENTS 800nA Operating Current, 1.25V/2.5V/4.096V 0.3μ Drives 0.01μ ...