MAX24287EVKIT Maxim Integrated Products, MAX24287EVKIT Datasheet
MAX24287EVKIT
Specifications of MAX24287EVKIT
Related parts for MAX24287EVKIT
MAX24287EVKIT Summary of contents
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... Common Usage Scenarios ♦ Optional Software Control Through MDIO Interface ♦ GPIO Pins Can Be Configured as Clocks, PIN-PACKAGE Status Signals and Interrupt Outputs ♦ 1.2V Operation with 3.3V I/O 68 TQFN-EP* ♦ Small, 8mm x 8mm, 68-Pin TQFN Package MAX24287 Highlighted Features Maxim Integrated Products 1 ...
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APPLICATION EXAMPLES ............................................................................................................. 6 2. BLOCK DIAGRAM ........................................................................................................................... 7 3. DETAILED FEATURES ................................................................................................................... 7 4. ACRONYMS, ABBREVIATIONS, AND GLOSSARY ...................................................................... 8 5. PIN DESCRIPTIONS ........................................................................................................................ 8 6. FUNCTIONAL DESCRIPTION ....................................................................................................... 16 6 ONFIGURATION 6.2 ...
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BMCR ................................................................................................................................................... 42 7.2.2 BMSR ................................................................................................................................................... 43 7.2.3 ID1 and ID2 .......................................................................................................................................... 44 7.2.4 AN_ADV ............................................................................................................................................... 45 7.2.5 AN_RX ................................................................................................................................................. 45 7.2.6 AN_EXP ............................................................................................................................................... 45 7.2.7 EXT_STAT ........................................................................................................................................... 46 7.2.8 JIT_DIAG ............................................................................................................................................. 46 7.2.9 PCSCR ................................................................................................................................................. 47 7.2.10 ...
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Figure 2-1. Block Diagram ........................................................................................................................................... 7 Figure 6-1. MDIO Slave State Machine ..................................................................................................................... 20 Figure 6-2. Management Information Flow Options, Case 1,Tri-Mode PHY ............................................................. 21 Figure 6-3. Management Information Flow Options, Case 2, SGMII Switch Chip .................................................... 21 Figure ...
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Table 5-1. Pin Type Definitions .................................................................................................................................... 8 Table 5-2. Detailed Pin Descriptions – Global Pins (3 Pins) ....................................................................................... 8 Table 5-3. Detailed Pin Descriptions – MDIO Interface (2 Pins) ................................................................................. 9 Table 5-4. Detailed Pin Descriptions – JTAG Interface ...
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Application Examples a) Copper Media <GMII> RXD[7:0] Processor, M RX_CLK 125 MHz ASIC, A 24287 TXD[7:0] FPGA C TX_CLK 125 MHz b) Connect Parallel MII Component to SGMII Component <GMII> RXD[7:0] Processor, M RX_CLK 125 MHz ASIC, A ...
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Block Diagram Figure 2-1. Block Diagram MAX24287 Receive RXD[7:0] RXCLK GMII RX_DV RGMII RX_ER TBI COL CRS RTBI MII Transmit GMII TXD[7:0] RGMII GTXCLK TBI TXCLK RTBI TX_EN TX_ER MII Control MDIO MDC and RST_N Status ALOS 3. ...
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Acronyms, Abbreviations, and Glossary • DCE Data Communication Equipment • DDR Dual Data Rate (data driven and latched on both clock edges) • DTE Data Terminating Equipment • PCB Printed Circuit Board • PHY Physical. Refers to either ...
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Table 5-3. Detailed Pin Descriptions – MDIO Interface (2 Pins) Pin Name PIN # Type MDC 41 I MDIO 42 IOz Table 5-4. Detailed Pin Descriptions – JTAG Interface (5 pins) Pin Name PIN # Type JTRST_N 43 I ...
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Pin Name PIN # Type GPIO4/TXD[4] 52 IOz GPIO5/TXD[5] 53 IOz GPIO6/TXD[6] 54 IOz GPIO7/TXD[7] 55 IOz Table 5-6. Detailed Pin Descriptions – SGMII/1000BASE-X Serial Interface (7 pins) Pin Name PIN # Type TDP, 9 Odiff TDN 8 TCLKP, ...
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Table 5-7. Detailed Pin Descriptions – Parallel Interface (25 pins) Pin Name PIN # Type RXCLK 40 IO RXD[0] 38 IOr RXD[1] 37 IOr RXD[2] 36 IOr RXD[3] 35 IOr RXD[4] 34 IOr RXD[5] 33 IOr RXD[6] 32 IOr ...
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Pin Name PIN # Type RX_DV 29 IOr RX_ER 28 IOr COL 27 IOr Pin Description Receive Data Valid During reset this pin is a configuration input. See section 6.1. After reset it is driven as an output. MII ...
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Pin Name PIN # Type CRS/COMMA 26 IOr TXCLK RXCLK1 GTXCLK 66 I Pin Description Carrier Sense / Comma Detect During reset this pin is a configuration input. See section 6.1. After reset it is driven as ...
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Pin Name PIN # Type TXD[ TXD[ TXD[ TXD[ TXD[4]/GPIO4 52 IOz TXD[5]/GPIO5 53 IOz TXD[6]/GPIO6 54 IOz TXD[7]/GPIO7 55 IOz TX_EN 57 I TX_ER 58 I Pin Description Transmit Data ...
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Table 5-8. Detailed Pin Descriptions – Power and Ground Pins (17 pins) Pin Name PIN # DVDD12 30, 56 Digital Power Supply, 1.2V (2 pins) DVDD33 20, 39, 65 Digital Power Supply, 3.3V DVSS 47 Return for DVDD12 and ...
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Functional Description 6.1 Pin Configuration During Reset The MAX24287 initial configuration is determined by pins that are sampled at reset. The values on these pins are used to set the reset values of several register bits. The pins ...
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Table 6-3. Reset Configuration Pins, 3-Pin Mode (COL=1) Pin Function CRS Double Date Rate GPO2 Serial Interface Note: In 3-pin mode register fields are automatically set as follows: REFCLK clock rate to 25MHz, GMIICR:SPD[1:0]=10, MDIO PHYAD is set to ...
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Table 6-6. GPIO4, GPIO5, GPIO6 and GPIO7 Configuration Options GPxx_SEL 000 High impedance, not driven, can be an used as an input 001 Drive logic 0 010 Drive logic 1 011 reserved value, do not use 100 Output 125MHz ...
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The PAGESEL interrupt routine to read the register without changing the MDIO page. 6.4 MDIO Interface 6.4.1 MDIO Overview The MAX24287's MDIO interface is compliant to IEEE 802.3 clause 22. MAX24287 always behaves as a PHY ...
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Figure 6-1. MDIO Slave State Machine OP=10 (read) TA-Z MDIO=Z TA-0 MDIO=0 DATA 16 bits MDIO=D[15:0] 16 clocks HW RESET PREAMBLE INIT MDIO=Z 32 consecutive 1s PREAMBLE / IDLE MDIO ...
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Examples of MAX24287 and PHY Management Using MDIO The MDIO interface is typically provided by the MAC function within a neighboring processor, ASIC or FPGA component. It can be used to configure the registers in the MAX24287 and/or ...
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Figure 6-4. Management Information Flow Options, Case 3, 1000BASE-X Interface MAC (GMII) 1000BASE-X Auto-negotiation GMII 1000BASE-X RXD[7:0] RX_CLK CDR 125MHz TXD[7:0] MAX24287 GTX_CLK 125MHz MDIO MAX24287 RD Optical Interface TD (e.g. SFP Module) 22 ...
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Serial Interface – 1000BASE-X or SGMII The high-speed serial interface is compatible with the specification of the 1000BASE-CX PMD service interface TP1 as defined in 802.3 clause 39 also compatible with the specification of the SGMII ...
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Parallel Interface – GMII, RGMII, TBI, RTBI, MII The parallel interface can be configured as GMII, MII or TBI compliant to IEEE 802.3 clauses 35, 22 and 36, respectively. It can also be configured as reduced pin count ...
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TBI Mode 6.6.2.1 Configuration The TBI and RTBI interfaces are used when a neighboring component implements the 802.3 PCS layer and therefore transmits and receives 10-bit 8B/10B-encoded data. The parallel interface can be configured for TBI mode using ...
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Pin Name 802.3 Pin Name TXD[7:0] tx_code_group[7:0] TX_EN tx_code_group[8] TX_ER tx_code_group[9] 6.6.2.4 Frequency-Locked Through Clocking, No Buffers The REFCLK signal is internally multiplied to produce the 1250MHz clock used to transmit data on the serial interface TDP/TDN pins. This ...
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COL=0, RXD[1:0]=xx, CRS=1 (xx=00 for RGMII-10, xx=01 for RGMII-100, xx=10 for RGMII-1000) • COL=1, CRS=1 For software configuration, the following register fields must be set: GMIICR.SPD[1:0]=xx and GMIICR.DDR=1 (where xx values are the same as shown above for ...
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Clocks The RXCLK clock output is 125MHz, 25MHz or 2.5MHz, depending on RGMII mode derived from the recovered clock from the receive serial data. The GTXCLK clock input must be 125MHz, 25MHz or 2.5MHz ±100 ppm. ...
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MII Mode The MAX24287's MII interface is compliant to IEEE 802.3 clause 22 except that TX_ER is ignored (and therefore the MAX24287 does not receive transmit error propagation from the MAC). The parallel interface can be configured for ...
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Auto-Negotiation (AN) In the MAX24287 the auto-negotiation mechanism described in IEEE 802.3 Clause 37 is used for auto-negotiation between IEEE 802.3 1000BASE-X link partners as well as the transfer of SGMII PHY status to a neighboring MAC as ...
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Figure 6-6. Auto-Negotiation with a Link Partner over 1000BASE-X <GMII> RXD[7:0] CDR RX_CLK 125 MHz MAX 24287 TXD[7:0] TX_CLK 125 MHz BASEX=1 The tx_Config_Reg and rx_Config_Reg format for 1000BASE-X auto-negotiation is shown in reserved bits are set to 0. ...
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Bit(s) Name 4:0 ZERO2 Table 6-15. AN_RX 1000BASE-X Auto-negotiation Ability Receive Register (MDIO 5) Bit(s) Name Acknowledge 13:12 RF 11:9 Reserved 8 4:0 Reserved 6.7.2 SGMII Control Information Transfer SGMII control ...
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Figure 6-8. SGMII Control Information Generation, Reception and Acknowledgement Speed Control - (a) PHY Initiated ETH Peripherial Speed Control - (b) Device Initiated (to allow Switch to connect to slower peripheral MAC devices) ETH Peripherial SDH/PDH Mapper The control ...
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Table 6-16. AN_ADV SGMII Configuration Information Register (MDIO 4) Bit(s) Name Reserved 13 ZERO1 12 DPLX 11:10 SPD[1:0] 9:1 ZERO2 0 ONE Note 1: See the AN_ADV register description. Table 6-17. AN_RX SGMII Configuration Information Receive ...
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Data Paths The MAX24287 data paths perform bidirectional conversion between a parallel interface (GMII, RGMII, TBI, RTBI or MII) and a 1.25Gbps serial interface (1000BASE-X or SGMII). In GMII, RGMII and MII modes, the data paths implement the ...
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For example, in GMII mode the transmit rate adaption buffer is written by GTXCLK and read by a 125MHz clock frequency locked to the REFCLK signal. If GTXCLK and REFCLK are both maintained within ±100ppm of nominal frequency then ...
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TX Rate Mode Buffer Mux MII 10 - DCE TX PLL 2.5 MII 10 - DTE TXCLK 2.5 TBI half rate GTXCLK 125 TBI full rate GTXCLK 125 RTBI GTXCLK 125 Table 6-20. Timing Path Muxes – RLB Loopback ...
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GPIO Pins as Clock Outputs Reference Clock. A 125MHz clock from the TX PLL (locked to the REFCLK signal) can be output on one or more GPIO pins. See section 6.2 for configuration details. One use for this ...
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During remote loopback the rate adaption buffers, PCS encoder and decoder, and PCS auto-negotiation function all operate normally. Loopback control bits BMCR.DLB and PCSCR.TLB must be set to zero for correct remote loopback operation. RLB cannot be used ...
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Figure 6-11. Recommended REFCLK Oscillator Wiring RST_N MAX24287 RST_N Oscillator REFCLK EN OUT 10k MAX24287 40 ...
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Register Descriptions The device registers can be accessed through the MDIO interface, which is part of the parallel MII interface. Registers at addresses are paged using the PAGESEL.PAGE register field. Register addresses ...
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BMCR Basic Mode Control Register (MDIO 0) Bit(s) Name 15 DP_RST 14 DLB 13 Reserved 12 AN_EN 11:10 Reserved 9 AN_START 8 Reserved 7 COL_TEST 6:0 Reserved Note 1: At reset when COL=1 or (RXD[1:0]!=11 and RX_DV=1) AN_EN ...
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BMSR Basic Mode Status Register (MDIO 1) Bit(s) Name 15 Reserved 14 SPD100FD 13 SPD100HD 12 SPD10FD 11 SPD10HD 10:9 Reserved 8 EXT_STAT 7 Reserved 6 MF_PRE 5 AN_COMP 4 RFAULT 3 AN_ABIL 2 LINK_ST 1 Reserved 0 ...
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ID1 and ID2 Registers ID1 and ID2 are set to all zeroes as allowed by clause 22.2.4.3.1 of IEEE 802.3. The actual device ID can be read from the ID register. Device ID 1 Register (MDIO 2) Bit(s) ...
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AN_ADV The register contents are transmitted to the link partner’s The fields of this register have different functions depending on whether the device is in 1000BASE-X auto- negotiation mode or in SGMII control information transfer mode. See section ...
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EXT_STAT Extended Status Register (MDIO 15) Bit(s) Name 15 1000X_FDX 14 1000X_HDX 13:0 Reserved 7.2.8 JIT_DIAG Jitter Diagnostics Register (MDIO 0.16) Bit(s) Name 15 JIT_EN 14:12 JIT_PAT 11:10 Reserved 9:0 CUST_PAT Description 1000BASE-X Full Duplex capability. Always indicates ...
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PCSCR PCS Control Register (MDIO 0.17) Bit(s) Name 15 Reserved 14 TIM_SHRT 13 DYRX_DIS 12 DYTX_DIS 11:7 Reserved 6 WD_DIS 5 Reserved 4 BASEX 3:2 Reserved 1 TLB 0 EN_CDET Note 1: At reset, if COL=1 or RXD[1] ...
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GMIICR GMII Interface Control Register (MDIO 0.18) Bit(s) Name 15:14 SPD[1:0] Selects parallel MII interface mode. See section 6.6. 13 TBI_RATE Select TBI bus receive clock mode. Used when SPD[1:0]=11; ignored otherwise. See section 6.6. TBI ...
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Note 5: At reset if COL=0 the TXCLK_EN bit is set to the value on the TXCLK pin, else TXCLK_EN is set other words, in 15-pin configuration mode the TXCLK_EN bit is set to the value ...
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IR This register contains both latched status bits and interrupt enable bits. When the latched status bit is active and the associated interrupt enable bit is set an interrupt signal can be driven onto one of the GPIO ...
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PAGESEL This page select register is used to extend the MDIO register space by mapping pages of 15 registers into MDIO register addresses 16 to 30. PAGESEL also has a global interrupt status bit. This ...
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ID The ID register matches the JTAG device ID (lower 12 bits) and revision (all 4 bits). Device ID Register (MDIO 1.16) Bit(s) Name REV REV[3:0] Device revision number. Contact factory for value. 15:12 11:0 DEVICE DEVICE[11:0] Device ...
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GPIOSR GPIO Status Register (MDIO 1.19) Bit(s) Name 15 Reserved 14 GPIO7L 13 GPIO6L 12 GPIO5L 11 GPIO4L 10 GPIO3L 9 GPIO2L 8 GPIO1L 7 Reserved 6 GPIO7 5 GPIO6 4 GPIO5 3 GPIO4 2 GPIO3 1 GPIO2 ...
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JTAG and Boundary Scan 8.1 JTAG Description The MAX24287 supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. contains the following items, which meet the requirements set by the ...
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Select-DR-Scan. All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the controller into the Capture-DR state and initiates a scan sequence. JTMS high moves the controller to the Select- IR-SCAN state. Capture-DR. ...
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JTCLK with JTMS low puts the controller in the Run-Test-Idle state. With JTMS high, the controller enters the Select-DR-Scan state. Figure 8-2. JTAG TAP Controller State Machine Test-Logic-Reset 1 0 Run-Test/Idle 0 8.3 JTAG Instruction Register ...
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SAMPLE/PRELOAD. SAMPLE/RELOAD is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. First, the digital I/Os of the device can be sampled at the boundary scan register, using the Capture-DR state, without interfering with the ...
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Electrical Characteristics ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Signal IO Lead with Respect to VSS ................................................................ -0.3V to +5.5V Supply Voltage (VDD12) Range with Respect to VSS ........................................................................ -0.3V to +1.32V Supply Voltage (VDD33) Range with Respect ...
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CMOS/TTL DC Characteristics Table 9-3. DC Characteristics for Parallel and MDIO Interfaces PARAMETER SYMBOL Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current, ...
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AC Electrical Characteristics Unless otherwise stated, all specifications in this section are valid for and T = -40°C to +85°C. A 9.3.1 REFCLK AC Characteristics Table 9-6. REFCLK AC Characteristics PARAMETER Frequency Accuracy Duty Cycle Rise Time (20−80%) ...
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Parallel Interface Receive AC Characteristics Figure 9-1. MII/GMII/RGMII/TBI/RTBI Receive Timing Waveforms Rx Clock RXD, RX_DV, RX_ER, COMMA Table 9-11. GMII and TBI Receive AC Characteristics PARAMETER RXCLK Period RXCLK, RXCLK1 Period 5 Rx Clock Duty Cycle 5 Rx ...
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Table 9-12. RGMII-1000 and RTBI Receive AC Characteristics PARAMETER SYMBOL RXCLK Period RXCLK Duty Cycle RXCLK to RXD, RX_CTL Delay Rise Time, All RX Signals Fall Time, All RX Signals Note 1: Per the RGMII spec, duty cycle may ...
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Table 9-15. MII–DTE Receive AC Characteristics PARAMETER SYMBOL RXCLK Period RXCLK Duty Cycle RXCLK to RXD, RX_DV, RX_ER Delay Note 1: RXCLK is an input in this mode. Note 2: 802.3 specifies setup and hold times, but setup and ...
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Table 9-17. RGMII-10/100 Transmit AC Characteristics PARAMETER SYMBOL GTXCLK Period GTXCLK Duty Cycle (Note 3) TXD, TX_CTL to GTXCLK Setup Time GTXCLK to TXD, TX_CTL Hold Time Rise Time, All TX Signals, 0.5V to 2.0V Fall Time, All TX ...
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MDIO Interface AC Characteristics Table 9-20. MDIO Interface AC Characteristics Parameter MDC Input Period (12.5MHz) MDC Input High MDC Input Low MDIO Input Setup Time to MDC MDIO Input Hold Time from MDC MDC to MDIO Output Delay ...
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JTAG Interface AC Characteristics Table 9-21. JTAG Interface Timing PARAMETER JTCLK Clock Period JTCLK Clock High/Low Time (Note 1) JTCLK to JTDI, JTMS Setup Time JTCLK to JTDI, JTMS Hold Time JTCLK to JTDO Delay JTCLK to JTDO ...
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Pin Assignments GVSS CVDD33 CVDD12 CVSS TCLKN TCLKP TVDD33 TDN TDP TVSS TVDD12 RVDD33 RDP RDN RVSS RVDD12 N.C. 17 N.C. = Not connected internally MAX24287 ...
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Package and Thermal Information For the latest package outline information and land patterns (footprints www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time 2011 Maxim Integrated Products DESCRIPTION Maxim is a registered trademark of Maxim Integrated Products. MAX24287 PAGES CHANGED — ...