MC10EP139 ON Semiconductor, MC10EP139 Datasheet

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MC10EP139

Manufacturer Part Number
MC10EP139
Description
Clock Generation Chip
Manufacturer
ON Semiconductor
Datasheet

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MC10EP139, MC100EP139
3.3V / 5V ECL ÷2/4, ÷4/5/6
Clock Generation Chip
Description
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or single−ended ECL or, if positive power supplies are used,
LVPECL input signals. In addition, by using the V
source can be AC coupled into the device. If a single−ended input is to be
used, the V
to ground via a 0.01 mF capacitor.
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen with
an asynchronous control. The internal enable flip−flop is clocked on the
falling edge of the input clock, therefore, all associated specification
limits are referenced to the negative edge of the clock input.
therefore, for systems which utilize multiple EP139s, the master reset
(MR) input must be asserted to ensure synchronization. For systems
which only use one EP139, the MR pin need not be exercised as the
internal divider design ensures synchronization between the ÷2/4 and the
÷4/5/6 outputs of a single device. All V
externally connected to power supply to guarantee proper operation.
Features
© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 7
The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip
The common enable (EN) is synchronous so that the internal dividers
Upon start−up, the internal flip−flops will attain a random state;
The 100 Series contains temperature compensation.
with V
with V
Maximum Frequency > 1.0 GHz Typical
50 ps Output−to−Output Skew
PECL Mode Operating Range: V
NECL Mode Operating Range: V
Open Input Default State
Safety Clamp on Inputs
Synchronous Enable/Disable
Master Reset for Synchronization of Multiple Chips
V
Pb−Free Packages are Available
BB
Output
EE
EE
BB
= −3.0 V to −5.5 V
= 0 V
output should be connected to the CLK input and bypassed
CC
CC
= 3.0 V to 5.5 V
= 0 V
CC
and V
BB
output, a sinusoidal
EE
pins must be
1
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
*For additional marking information, refer to
DW SUFFIX
CASE 948E
CASE 751D
MN SUFFIX
CASE 485E
Application Note AND8002/D.
TSSOP−20
DT SUFFIX
(Note: Microdot may be in either location)
SOIC−20
QFN−20
1
ORDERING INFORMATION
HEP
KEP
XXX
A
L,WL
Y, YY
W, WW = Work Week
G or G
1
http://onsemi.com
= MC10EP
= MC100EP
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Pb−Free Package
20
Publication Order Number:
1
1
DIAGRAMS*
HEP or KEP
MARKING
20
MCXXXEP139
ALYWG
AWLYYWWG
ALYWG
EP139
139
XXXX
MC10EP139/D
G
G

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MC10EP139 Summary of contents

Page 1

... MC10EP139, MC100EP139 3. ECL ÷2/4, ÷4/5/6 Clock Generation Chip Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single− ...

Page 2

Warning: All V and V pins must be externally connected Power Supply to guarantee proper ...

Page 3

DIVSELa CLK CLK EN MR DIVSELb0 DIVSELb1 V EE Table 2. FUNCTION TABLES Z = Low−to−High Transition ZZ = High−to−Low Transition DIVSELa DIVSELb0 CLK Q (÷2) Q (÷4) Q (÷5) Q (÷6) Figure 3. CLK and OUTPUT Timing Diagram CLK ...

Page 4

Table 3. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see ...

Page 5

Table 5. 10EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 6

Table 7. 10EP DC CHARACTERISTICS, NECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 7

Table 9. 100EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note 15 Output LOW Voltage (Note 15 Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 8

Table 11. AC CHARACTERISTICS V Symbol Characteristic f Maximum Frequency max (See Figure 5 F /JITTER) max t , Propagation Delay CLK, Q (Diff) PLH t PHL t Reset Recovery RR t Setup Time s DIVSEL, CLK t Hold Time ...

Page 9

900 800 700 600 500 400 300 200 (JITTER) 100 É É É É É É É É É É É É É É É É É É É É 0 É É É É É É É É É ...

Page 10

900 800 700 600 500 400 300 200 (JITTER) 100 É É É É É É É É É É É É É É É É É É É É 0 É É É É É É É É É ...

Page 11

... ORDERING INFORMATION Device MC10EP139DT MC10EP139DTG MC10EP139DTR2 MC10EP139DTR2G MC10EP139DW MC10EP139DWG MC10EP139DWR2 MC10EP139DWR2G MC10EP139MNG MC10EP139MNTXG MC100EP139DT MC100EP139DTG MC100EP139DTR2 MC100EP139DTR2G MC100EP139DW MC100EP139DWG MC100EP139DWR2 MC100EP139DWR2G MC100EP139MNG MC100EP139MNTXG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb− ...

Page 12

... 0.100 (0.004) −T− SEATING PLANE 16X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−20 CASE 948E−02 ISSUE ...

Page 13

20X T 0. 18X A1 T PACKAGE DIMENSIONS SOIC−20 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D−05 ISSUE G q SEATING PLANE C http://onsemi.com 13 ...

Page 14

... G 0.50 BSC 0.020 BSC H 1.38 1.43 0.054 0.056 J 0.20 REF 0.008 REF K 0.00 0.05 0.000 0.002 L 0.35 0.45 0.014 0.018 M 2.00 BSC 0.079 BSC N 2.00 BSC 0.079 BSC P 1.38 1.43 0.054 0.056 R 0.60 0.80 0.024 0.031 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC10EP139/D ...

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