MC14042B ON Semiconductor, MC14042B Datasheet

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MC14042B

Manufacturer Part Number
MC14042B
Description
Quad Transparent Latch
Manufacturer
ON Semiconductor
Datasheet

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MC14042B
Quad Transparent Latch
P–channel and N–channel enhancement mode devices in a single
monolithic structure. Each latch has a separate data input, but all four
latches share a common clock. The clock polarity (high or low) used to
strobe data through the latches can be reversed using the polarity
input. Information present at the data input is transferred to outputs Q
and Q during the clock level which is determined by the polarity input.
When the polarity input is in the logic “0” state, data is transferred
during the low clock level, and when the polarity input is in the logic
“1” state the transfer occurs during the high clock level.
2. Maximum Ratings are those values beyond which damage to the device
3. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
to the range V
either V
MAXIMUM RATINGS
March, 2000 – Rev. 3
Symbol
V
The MC14042B Quad Transparent Latch is constructed with MOS
I
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
Schottky TTL Load Over the Rated Temperature Range
Buffered Data Inputs
Common Clock
Clock Polarity Control
Q and Q Outputs
Double Diode Input Protection
Supply Voltage Range = 3.0 Vdc to 1 8 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
in
in
Semiconductor Components Industries, LLC, 2000
may occur.
Plastic “P and D/DW” Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C
V
T
P
, V
, I
T
T
stg
DD
D
A
L
out
out
SS
or V
DC Supply Voltage Range
Input or Output Voltage Range
Input or Output Current
Power Dissipation,
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
SS
DD
(DC or Transient)
(DC or Transient) per Pin
per Package (Note 3.)
(8–Second Soldering)
v
). Unused outputs must be left open.
(V
in
Parameter
or V
(Voltages Referenced to V
out
)
v
V
DD
.
in
and V
– 0.5 to V
– 0.5 to +18.0
SS
– 55 to +125
– 65 to +150
out
) (Note 2.)
Value
500
260
should be constrained
10
DD
+ 0.5
1
Unit
mW
mA
V
V
C
C
C
1. For ordering information on the EIAJ version of
MC14042BCP
MC14042BD
MC14042BDR2
MC14042BF
MC14042BFEL
MC14042BFR1
MC14042BFR2
the SOIC packages, please contact your local
ON Semiconductor representative.
Device
ORDERING INFORMATION
A
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
http://onsemi.com
CASE 751B
SOEIAJ–16
CASE 648
CASE 966
P SUFFIX
D SUFFIX
F SUFFIX
SOIC–16
SOEIAJ–16
SOEIAJ–16
SOEIAJ–16
SOEIAJ–16
PDIP–16
= Assembly Location
Package
SOIC–16
SOIC–16
PDIP–16
Publication Order Number:
2500/Tape & Reel
16
16
16
1
1
1
MC14042BCP
DIAGRAMS
MARKING
See Note 1.
See Note 1.
See Note 1.
See Note 1.
AWLYYWW
MC14042B
AWLYWW
AWLYWW
Shipping
2000/Box
2400/Box
MC14042B/D
14042B

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MC14042B Summary of contents

Page 1

... MC14042B Quad Transparent Latch The MC14042B Quad Transparent Latch is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Each latch has a separate data input, but all four latches share a common clock. The clock polarity (high or low) used to strobe data through the latches can be reversed using the polarity input ...

Page 2

... MC14042B PIN ASSIGNMENT CLOCK POLARITY TRUTH TABLE Clock Polarity Data 1 0 Latch 1 1 Data 0 1 Latch LOGIC DIAGRAM D0 LATCH CLOCK POLARITY 6 D1 LATCH ...

Page 3

... I (50 pF – 50) Vfk where (per package pF MC14042B (Voltages Referenced Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î – Î Î Î ...

Page 4

... For Power Dissipation test, each output is loaded with capacitance Figure 1. AC and Power Dissipation Test Circuit and Timing Diagram MC14042B = pF Î Î Î Î Î Î Î Î Î Î Î Î Î Symbol ...

Page 5

... CLOCK INPUT 10% P. 90% DATA INPUT t P. PLH Q OUTPUT 90% 50% 10% *Input clock rise time except for maximum rise time test. Figure 2. AC Test Circuit and Timing Diagram (Clock to Output) http://onsemi.com MC14042B CLOCK POLARITY ...

Page 6

... G K –T– SEATING PLANE 0.25 (0.010 MC14042B PACKAGE DIMENSIONS PDIP–16 P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R L SEATING –T– PLANE SOIC–16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B– ...

Page 7

... PLASTIC EIAJ SOIC PACKAGE VIEW 0.10 (0.004) 0.13 (0.005) M MC14042B PACKAGE DIMENSIONS SOEIAJ–16 F SUFFIX CASE 966–01 ISSUE O NOTES DETAIL P c http://onsemi.com 7 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. ...

Page 8

... Email: ONlit–asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549 Phone: 81–3–5740–2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 MC14042B/D ...

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