MC74HC4020A ON Semiconductor, MC74HC4020A Datasheet

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MC74HC4020A

Manufacturer Part Number
MC74HC4020A
Description
14-Stage Binary Ripple Counter High-Performance Silicon-Gate CMOS
Manufacturer
ON Semiconductor
Datasheet

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MC74HC4020A
14−Stage Binary Ripple
Counter
High−Performance Silicon−Gate CMOS
MC14020B. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
brought out to pins. The output of each flip−flop feeds the next and the
frequency at each output is half of that of the preceding one. Reset is
asynchronous and active−high.
of internal ripple delays. Therefore, decoded output signals are subject
to decoding spikes and may have to be gated with the Clock of the
HC4020A for some designs.
Features
*For additional information on our Pb−Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2005
June, 2005 − Rev. 4
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
The MC74C4020A is identical in pinout to the standard CMOS
This device consists of 14 master−slave flip−flops with 12 stages
State changes of the Q outputs do not occur simultaneously because
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With JEDEC Standard No. 7A Requirements
Chip Complexity: 398 FETs or 99.5 Equivalent Gates
Pb−Free Packages are Available*
1
16
16
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
16
16
1
1
1
1
ORDERING INFORMATION
A
L, WL
Y, YY
W, WW
G
G
(Note: Microdot may be in either location)
http://onsemi.com
CASE 751B
CASE 948F
SOEIAJ−16
TSSOP−16
DT SUFFIX
CASE 648
CASE 966
N SUFFIX
D SUFFIX
F SUFFIX
PDIP−16
SOIC−16
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
= Pb−Free Package
Publication Order Number:
16
16
1
1
16
1
MC74HC4020AN
MC74HC4020A/D
DIAGRAMS
AWLYYWWG
16
1
MARKING
HC4020AG
74HC4020A
AWLYWW
ALYWG
ALYWG
HC40
20A
G

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MC74HC4020A Summary of contents

Page 1

... Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. 1 MARKING DIAGRAMS 16 MC74HC4020AN AWLYYWWG 1 16 HC4020AG AWLYWW 1 16 HC40 20A ALYWG 74HC4020A ALYWG 1 Publication Order Number: MC74HC4020A/D ...

Page 2

... MC74HC4020AN MC74HC4020ANG MC74HC4020AD MC74HC4020ADG MC74HC4020ADR2 MC74HC4020ADR2G MC74HC4020ADTR2 MC74HC4020ADTR2G MC74HC4020AF MC74HC4020AFG MC74HC4020AFEL MC74HC4020AFELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. MC74HC4020A Clock Q1 Q4 ...

Page 3

... Maximum Low−Level Input Voltage IL V Minimum High−Level Output Voltage Maximum Low−Level Output Voltage V OL MC74HC4020A Î Î Î Î Î Î Î Î Value Unit Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 4

... [93.7 + 59.3 (n−1 3 [61.5 + 34.4 (n−1 Power Dissipation Capacitance (Per Package Used to determine the no−load dynamic power consumption Semiconductor High−Speed CMOS Data Book (DL129/D). MC74HC4020A Condition Condition | ≤ 2.4mA out | ≤ 4.0mA |I out | ≤ ...

Page 5

... MAX t t PHL PLH 90% Q1 50% 10% t TLH Figure 3. MC74HC4020A = 6 ns) Parameter PIN DESCRIPTIONS OUTPUTS Q1, Q4—Q14 (Pins 13, 12, 14, 15 Active−high outputs. Each Qn output divides the Clock input frequency by 2 SWITCHING WAVEFORMS Clock V CC GND Reset Any Q ...

Page 6

... Qn 50% t PLH Qn+1 50% Figure Clock Reset Q6 = Pin Pin Pin 13 MC74HC4020A SWITCHING WAVEFORMS (continued GND t PHL Pin 12 Q10 = Pin 14 Q11 = Pin 15 Figure 7. Expanded Logic Diagram http://onsemi.com 6 TEST POINT ...

Page 7

... NOTE: Ground MUST be isolated by a transformer or opto−isolator for safety reasons. MC74HC4020A 128 256 Figure 8. Timing Diagram APPLICATIONS INFORMATION feeds the HC4020A. Selecting outputs Q5, Q10, Q11, and Q12 causes a reset every 3600 clocks. The HC20 decodes the counter outputs, produces a single (narrow) output pulse, and resets the binary counter ...

Page 8

... PL 0.25 (0.010) M −A− −B− −T− SEATING PLANE 0.25 (0.010 MC74HC4020A PACKAGE DIMENSIONS PDIP−16 N SUFFIX CASE 648−08 ISSUE T L SEATING −T− PLANE SOIC−16 D SUFFIX CASE 751B−05 ISSUE ...

Page 9

... L PIN 1 IDENT. 1 0.15 (0.006 −V− C 0.10 (0.004) SEATING −T− D PLANE MC74HC4020A PACKAGE DIMENSIONS TSSOP−16 DT SUFFIX CASE 948F−01 ISSUE Ç Ç Ç 9 É É É Ç Ç Ç J1 É É É Ç Ç Ç ...

Page 10

... BSC H 7.40 8.20 0.291 0.323 E L 0.50 0.85 0.020 0.033 L 1.10 1.50 0.043 0.059 0.70 0.90 0.028 0.035 1 Z −−− 0.78 −−− 0.031 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. MC74HC4020A/D ...

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