mpc93r51 Integrated Device Technology, mpc93r51 Datasheet

mpc93r51

Manufacturer Part Number

mpc93r51

Description

Low Voltage Pll Clock Driver

Manufacturer

Integrated Device Technology

Datasheet

1.MPC93R51.pdf (12 pages)

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IDT™ Low Voltage PLL Clock Driver

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

Low Voltage PLL Clock Driver

Freescale Semiconductor

Technical Data

This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

Low Voltage PLL Clock Driver

high performance clock distribution systems. With output frequencies of up to

240 MHz and a maximum output skew of 150 ps, the MPC93R51 is an ideal

solution for the most demanding clock tree designs. The device offers 9 low skew

clock outputs, each is configurable to support the clocking needs of the various

high-performance microprocessors including the PowerQuicc II integrated

communication microprocessor. The devices employ a fully differential PLL

design to minimize cycle-to-cycle and long-term jitter.

Features

•

Functional Description

operation of the MPC93R51 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback

path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be

selected to match the VCO frequency range. With available output dividers of divide-by-4 and divide-by-8, the internal VCO of

the MPC93R51 is running at either 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs

is either the one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using

the FSELA, FSELB, FSELC and FSELD pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2

and 1:4. The REF_SEL pin selects the differential LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input

(TCLK). The MPC93R51 also provides a static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test

mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended

for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency specification

does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes

the PLL to loose lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase

locked loop, also enabling the PLL to recover to normal operation. The MPC93R51 is 3.3 V compatible and requires no external

loop filter components. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS compatible

levels with the capability to drive terminated 50 Ω transmission lines. For series terminated transmission lines, each of the

MPC93R51 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a

7x7 mm

Application Information

essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase

offset between the outputs and the reference signal.

Freescale Confidential Proprietary, NDA Required / Preliminary

The MPC93R51 is a 3.3 V compatible, PLL based clock generator targeted for

The MPC93R51 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal

The fully integrated PLL of the MPC93R51 allows the low skew outputs to lock onto a clock input and distribute it with

25–240 MHz output frequency range

Fully integrated PLL

Compatible to various microprocessors such as PowerQuicc II

Supports networking, telecommunications and computer applications

Configurable outputs: divide-by-2, 4 and 8 of VCO frequency

LVPECL and LVCMOS compatible inputs

External feedback enables zero-delay configurations

Output enable/disable and static test mode (PLL enable/disable)

Low skew characteristics: maximum 150 ps output-to-output

Cycle-to-cycle jitter max. 22 ps RMS

32-lead LQFP package

32-lead Pb-free Package Available

Ambient Temperature Range 0°C to +70°C

Pin & Function Compatible with the MPC951

9 outputs LVCMOS PLL clock generator

32-lead LQFP package.

PLL CLOCK GENERATOR

32-LEAD LQFP PACKAGE

LOW VOLTAGE 3.3 V

Pb-FREE PACKAGE

CASE 873A-03

FA SUFFIX

AC SUFFIX

DATA SHEET

Rev. 4, 1/2005

MPC93R51

Related parts for mpc93r51

mpc93r51 Summary of contents

Page 1

... VCO frequency range. With available output dividers of divide-by-4 and divide-by-8, the internal VCO of the MPC93R51 is running at either the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is either the one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB, FSELC and FSELD pins, respectively ...

Page 2

... FSELA (Pulldown) FSELB (Pulldown) FSELC (Pulldown) FSELD (Pulldown) OE The MPC93R51 requires an external RC filter for the analog power supply pin V PLL_EN REF_SEL MPC93R51 IDT™ Low Voltage PLL Clock Driver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc ÷ ...

Page 3

... PLL enabled. The VCO output is routed to the output dividers Outputs disabled, PLL loop is open VCO is forced to its minimum frequency QA = VCO ÷ VCO ÷ VCO ÷ VCO ÷ 8 Max Unit Condition ±20 mA ±50 mA 150 °C MPC93R51 MPC93R51 3 ...

Page 4

... Functional operation is obtained when the crosspoint is within the V CMR and the input swing lies within the V 2. The MPC93R51 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage of V MPC93R51 IDT™ ...

Page 5

... Normal AC operation is obtained when the crosspoint is within the V CMR and the input swing lies within the V 4. The MPC93R51 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t are within the specified range. IDT™ Low Voltage PLL Clock Driver ...

Page 6

... Freescale MC100EP111 or MC10EP222, taking advantage of its superior low-skew performance. Clock trees using LVPECL for clock distribution and the MPC93R51 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. ...

Page 7

... Advanced Clock Drivers Devices Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor the lowest VCO frequency (200 MHz for the MPC93R51). Applications using a higher VCO frequency exhibit less I/O jitter than the AC characteristic limit. The I/O jitter characteristics in ...

Page 8

... Figure 7 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC93R51 clock driver is effectively doubled due to its capability to drive multiple lines. MPC93R51 IDT™ ...

Page 9

... TIME (ns) Figure 8. Single versus Dual Waveforms Pulse Generator Z = 50Ω Figure 10. TCLK MPC93R51 AC Test Reference for V Differential Pulse Generator Z = 50Ω IDT™ Low Voltage PLL Clock Driver Advanced Clock Drivers Devices Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc ...

Page 10

... Figure 15. Output-to-Output Skew t SK( –1/f JIT(PER Figure 17. Period Jitter V =3 2.4 0. Figure 19. Transition Time Test Reference Advanced Clock Drivers Devices Freescale Semiconductor NETCOM V CC ÷ GND V CC ÷ GND ÷ GND V CC ÷ GND | MPC93R51 ...

Page 11

... EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1-mm AND 0.25-mm FROM THE LEAD TIP. c1 MILLIMETERS DIM MIN MAX A 1.40 1.60 A1 0.05 0. 1.35 1.45 b 0.30 0. 0.30 0.40 c 0.09 0.20 c1 0.09 0.16 D 9.00 BSC D1 7.00 BSC e 0.80 BSC E 9.00 BSC E1 7.00 BSC L 0.50 0.70 L1 1.00 REF q 0˚ 7˚ REF R1 0.08 0.20 R2 0.08 --- 0.20 REF S MPC93R51 NETCOM MPC93R51 11 ...

Page 12

... MPC92459 MPC93R51 PART NUMBERS 900 MHz Low Voltage LVDS Clock Synthesizer Low Voltage PLL Clock Driver INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. ...

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