mx28f1000p Macronix International Co., mx28f1000p Datasheet

Page 1

... Block Erase • Optimized high density blocked architecture – Four 4-KB blocks GENERAL DESCRIPTION The MX28F1000P is a 1-mega bit Flash memory or- ganized as 128K bytes of 8 bits each. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX28F1000P is packaged in 32-pin PDIP, PLCC and TSOP ...

Page 2

... MX28F1000P Block Address and Block Structure A16 A15 A14 A13 P/N: PM0340 A12 16k X X 16k X X 16k X X 16k ...

Page 3

... MX28F1000P (NORMAL TYPE MX28F1000P (REVERSE TYPE) PIN NAME Address Input Data Input/Output Chip Enable Input Output Enable Input Write enable Pin Program Supply Voltage Power Supply Pin (+5V) Ground Pin REV ...

Page 4

... BLOCK DIAGRAM CE CONTROL OE INPUT WE LOGIC ADDRESS LATCH A0-A16 AND BUFFER Q0-Q7 P/N: PM0340 MX28F1000P PROGRAM/ERASE HIGH VOLTAGE MX28F1000P FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV PROGRAM DATA LATCH I/O BUFFER 4 MODE LOGIC STATE REGISTER COMMAND DATA DECODER COMMAND DATA LATCH REV. 1.6, JAN. 19, 1999 ...

Page 5

... During write cycles, the command register internally latches address and data needed for the programming and erase operations. For system design simplifica- tion, the MX28F1000P is designed to support either controlled writes. During a system write cycle, addresses are latched on the falling edge whichever occurs last ...

Page 6

... Write X 00H Write X 90H Write X 30H Write X 20H Write X 40H Write X 20H Write X 60H Write EVA A0H Write X FFH 6 MX28F1000P SECOND BUS CYCLE OPERATION ADDRESS DATA Read IA ID Write X 30H Write EA D0H Write PA PD Write X 20H Write EA 60H Read X EVD Write X FFH REV ...

Page 7

... Placing high voltage on the VPP pin enables read/write operations. Device operations are selected by writing specific data patterns into the command register. Ta- ble 1 defines these MX28F1000P register commands. Table 2 defines the bus operations of MX28F1000P. TABLE 2. MX28F1000P BUS OPERATIONS OPERATION READ-ONLY Read ...

Page 8

... This default value ensures that no spurious alteration of memory contents occurs during the VPP power transition. Where the VPP supply is hard-wired to the MX28F1000P, the device powers up and remains enabled for reads until the command register contents are changed. SILICON-ID-READ COMMAND Flash-memories are intended for use in applications where the local CPU alters memory contents ...

Page 9

... After each erase operation, all bytes must be verified. The erase verify operation is initiated by writing A0H into the command register. The address for the byte to be verified must be supplied latched on the falling edge of the WE pulse. 9 MX28F1000P The erase REV. 1.6, JAN. 19, 1999 ...

Page 10

... The Data Polling feature is active during Automatic Program/Erase algorithms. POWER-UP SEQUENCE The MX28F1000P powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of a two-step command sequence. Power up sequence is not required. ...

Page 11

... TYP MIN. TYP 1 1 -0.3 (NOTE 1) 2.4 2.4 3. Test condition: TA =-40°C to 85°C, Vcc = 5V±10%, Vpp = GND to Vcc 100pF(for MX28F1000P-90/12 -40°C to 85°C, Vcc = 5V±10%, Vpp = GND to Vcc 35pF(for MX28F1000P-70) 4.ICC1=35mA for TA=-40°C to 85°C 11 MX28F1000P MAX. UNIT CONDITIONS 14 pF VIN = 0V ...

Page 12

... Note1 NOTE: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. ACTIVE MODE tCE tOE tACC 12 MX28F1000P 28F1000P-12 MIN. MAX. UNIT CONDITIONS 120 ns CE=OE=VIL 120 ns OE=VIL 50 ns CE=VIL CE=VIL ...

Page 13

... VCC must be applied before VPP and removed after VPP. 2. VPP must not exceed 14V including overshoot influence may be had upon device reliability if the device is installed or removed while VPP=12V not alter VPP either VIL to 12V or 12V to VIL when CE=VIL. P/N: PM0340 MX28F1000P MIN. TYP MAX. UNIT 10 uA ...

Page 14

... MX28F1000P 28F1000P-12 MAX. MIN. MAX. UNIT CONTIONS 100 ns 100 ns 120 100 100 100 ...

Page 15

... CL = 100 pF including jig capacitance(35pF for 70 ns parts) SWITCHING TEST WAVEFORMS 2 TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". P/N: PM0340 CL 6.2K ohm 2.0V TEST POINTS 0.8V INPUT Input pulse rise and fall times are <20ns. 15 MX28F1000P 1.8K ohm +5V DIODES = IN3064 OR EQUIVALENT 2.0V 0.8V OUTPUT REV. 1.6, JAN. 19, 1999 ...

Page 16

... Auto program & DATA polling program command Address valid tAS tAVT tCWC tCEPH1 tCESP tCES tCEP tCEP tDS tDH tDS tDH tDPA Command in Data in DATA polling Command in Data in Command #40H 16 MX28F1000P tVPH tAH1 tCESC tDF DATA DATA DATA REV. 1.6, JAN. 19, 1999 ...

Page 17

... AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART P/N: PM0340 START Apply VppH Write Set up auto program Command (40H) Write Auto program Command(A/D) NO Toggle Bit Checking DQ6 not Toggled YES NO Verify Byte Ok YES NO Last Byte YES Auto Program Completed 17 MX28F1000P Reset Auto Program Failed REV. 1.6, JAN. 19, 1999 ...

Page 18

... Setup auto chip erase/ Auto chip erase & DATA polling erase command tAETC tCWC tCESP tCES tCEP tCEP tCEPH1 tDS tDH tDS tDH tDPA Command in Command in DATA polling Command in Command in Command #30H Command #30H 18 MX28F1000P tVPH tCESC tDF REV. 1.6, JAN. 19, 1999 ...

Page 19

... AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART P/N: PM0340 START Apply VppH Write Set up auto chip Erase Command (30H) Write Auto chip Erase Command(30H) Toggle Bit Checking No DQ6 not Toggled YES DATA Polling No DQ7 = 1 YES Auto Chip Erase Completed 19 MX28F1000P Reset Auto Chip Erase Failed REV. 1.6, JAN. 19, 1999 ...

Page 20

... DATA polling, timing waveform) are in high impedance. Block Block address 0 address 1 tAH tBALC tBAL tCEP tCEPH2 tDH tDS tDH Command in Command in 20 MX28F1000P Auto block erase & DATA polling tVPH Block address # tAH1 tCESC tAETB tDF tDPA DATA polling REV. 1.6, JAN. 19, 1999 ...

Page 21

... Write Auto block Erase Command(D0H) to Load Block Address Load Block Address Last Block NO to Erase YES Wait 200us Toggle Bit Checking NO DQ6 not Toggled YES NO DATA Polling DQ7 = 1 YES Auto Block Erase Completed 21 MX28F1000P Reset Auto Block Erase Failed REV. 1.6, JAN. 19, 1999 ...

Page 22

... Setup chip erase/ Chip erase erase command tET tCWC tCEP tCEP tCEPH1 tDS tDH tDS tDH Command in Command in Command in Command in 22 MX28F1000P Erase Verify tVPH Verify Address tAS tAH tCESV tCESC tCEP tCES tVA tDH tDS tDF Command in Data valid Command in ...

Page 23

... VPP = VCC END BLOCK ERASE COMPLETE START Apply VPP = VPPH WRITE SETUP BLOCK ERASE COMMAND ( 60H ) WRITE BLOCK ERASE COMMAND ( LOAD FIRST SECTOR ADDRESS , 60H ) LOAD OTHER SECTORS' ADDRESS IF NECESSARY ( LOAD OTHER SECTOR ADDRESS ) WAIT 10 ms END 23 MX28F1000P N = N+1 NO REV. 1.6, JAN. 19, 1999 ...

Page 24

... ERASE VERIFY FLOW INCREMENT ADDRESS P/N: PM0340 MX28F1000P START APPLY VPP = VPPH ADDRESS = FIRST ADDRESS OF ERASED BLOCKS OR LAST VERIFY FAILED ADDRESS WRITE ERASE VERIFY COMMAND ( A0H ) WAIT ERSVFY FFH ? YES NO LAST ADDRESS ? YES ERASE VERIFY COMPLETE ERASE FLOW AGAIN OR ABORT ...

Page 25

... Q7 Command in Command in Q0~Q6 Command in Command in Command #60H Command #60H P/N: PM0340 Block erase Block Block address 1 address # tBALC tBAL tET tCEPH2 25 MX28F1000P Erase Verify tVPH Verify address Verify address tAS tAH tCESV tCESC tCEP tCES tDS tVA tDH tDF Command in Data valid Command in ...

Page 26

... VIL A10-A16 VIH P/N: PM0340 Address valid tCWC tACC tCEPH1 tCE tDH tOE 00H tACC tACC tCE tOE tOH Manufacturer code C2H 26 MX28F1000P tVPH tCESC tOES tDF tOH Data out valid tDF tOH Device code 1AH REV. 1.6, JAN. 19, 1999 ...

Page 27

... OE Q0-Q7 P/N: PM0340 Address Valid tCWC tACC tCEP tCEPH2 tCE tDH tDS tOE Command in 90H tCWC tCEP tCEP tCEPH1 tDS tDH tDS tDH Command in Command in FFH FFH 27 MX28F1000P tVPH tCESC tOES tDF tOH Data out valid C2H or 1AH REV. 1.6, JAN. 19, 1999 ...

Page 28

... PARAMETER Chip/Sector Erase Time Chip Programming Time Erase/Program Cycles Byte Program Time P/N: PM0340 TOGGLE BIT DATA POLLING DATA PROGRAM/ERASE COMPLETE LIMITS MIN. TYP. 1.5 2 10,000 15 28 MX28F1000P DATA DATA DATA DATA POLLING DATA MAX. UNITS 20 sec 13.8 sec cycles 642 us REV. 1.6, JAN. 19, 1999 ...

Page 29

... MX28F1000PQC-90C4 90 MX28F1000PQC-12C4 120 MX28F1000PTC-70C4 70 MX28F1000PTC-90C4 90 MX28F1000PTC-12C4 120 MX28F1000PRC-70C4 70 MX28F1000PRC-90C4 90 MX28F1000PRC-12C4 120 MX28F1000PPI-70 70 MX28F1000PPI-90 90 MX28F1000PPI-12 120 MX28F1000PQI-70 70 MX28F1000PQI-90 90 MX28F1000PQI-12 120 MX28F1000PTI-70 70 MX28F1000PTI-90 90 MX28F1000PTI-12 120 MX28F1000PRI-70 70 MX28F1000PRI-90 90 MX28F1000PRI-12 120 P/N: PM0340 MX28F1000P OPERATING STANDBY PACKAGE CURRENT CURRENT MAX.(mA) MAX.(uA) 50 100 32 Pin DIP 50 100 ...

Page 30

... K .46 [REF] .018 [REF] L 10.40/12.94 .410/.510 (W) (L) (W) (L) M .89R .035R N .25[Typ.] .010[Typ.] NOTE: Each lead certerline is located within .25mm[.01 inch] of its true position [TP maximum at maximum material condition. P/N: PM0340 MX28F1000P ...

Page 31

... K 1.00 ± .10 .039 ± .004 L 1.27 max. .050 max. M .50 .020 N 0 ~5° .500 NOTE: Each lead certerline is located within .25mm[.01 inch] of its true position [TP maximum at maximum material condition. P/N: PM0340 MX28F1000P REV. 1.6, JAN. 19, 1999 L ...

Page 32

... Fast access time 70ns added. 1.6 1)Absolute max. ratings:TA=-40°C to 85°C 2)DC Characteristics:ICC1=35mA for TA=-40°C to 85°C 3)AC Characteristics:TA=-40°C to 85°C 4)Order Informance:Add Industrial Grade 5)Erase & Programming Performance:New in Creased table P/N: PM0340 MX28F1000P Page P11 P14 P29 32 Date Dec/26/1996 JAN/19/1999 ...

Page 33

... TEL:+65-747-2309 FAX:+65-748-4090 TAIPEI OFFICE: TEL:+886-3-509-3300 FAX:+886-3-509-2200 ACRONIX MERICA, NC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com C L O., TD. MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice. 33 MX28F1000P ...