nb2309a ON Semiconductor, nb2309a Datasheet

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nb2309a

Manufacturer Part Number
nb2309a
Description
3.3 V Zero Delay Clock Buffer
Manufacturer
ON Semiconductor
Datasheet

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NB2309A
3.3 V Zero Delay
Clock Buffer
distribute high-speed clocks. It accepts one reference input and drives
out nine low-skew clocks. It is available in a 16 pin package.
has higher drive than the -1 devices. All parts have on-chip PLL's that
lock to an input clock on the REF pin. The PLL feedback is on-chip
and is obtained from the CLKOUT pad.
controlled by the Select inputs as shown in the Select Input Decoding
Table. If all the output clocks are not required, Bank B can be
three-stated. The select inputs also allow the input clock to be directly
applied to the outputs for chip and system testing purposes.
distribute it. In this case the skew between the outputs of the two
devices is guaranteed to be less than 700 ps.
and output propagation delay is guaranteed to be less than 350 ps, and
the output to output skew is guaranteed to be less than 250 ps.
in the ordering information table. The NB2309A1 is the base part. The
NB2309Ax1H* is the high drive version of the -1 and its rise and fall
times are much faster than -1 part.
Features
*x = I for Industrial.
© Semiconductor Components Industries, LLC, 2007
November, 2007 - Rev. 5
The NB2309A is a versatile, 3.3 V zero delay buffer designed to
The -1H version of the NB2309A operates at up to 133 MHz, and
The NB2309A has two banks of four outputs each, which can be
Multiple NB2309A devices can accept the same input clock and
All outputs have less than 200 ps of cycle-to-cycle jitter. The input
The NB2309A is available in two different configurations, as shown
PCI Bus Frequencies
Based Systems
15 MHz to 133 MHz Operating Range, Compatible with CPU and
Zero Input - Output Propagation Delay
Multiple Low-Skew Outputs
Output-Output Skew Less than 250 ps
Device-Device Skew Less than 700 ps
One Input Drives 9 Outputs, Grouped as 4 + 4 + 1
Less than 200 ps Cycle-to-Cycle Jitter is Compatible with PentiumR
Test Mode to Bypass PLL
Available in 16 Pin, 150 mil SOIC and 4.4 mm TSSOP
3.3 V Operation, Advanced 0.35 m CMOS Technology
Industrial Temprature Range
These are Pb-Free Devices
1
*For additional marking information, refer to
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Application Note AND8002/D.
16
CASE 751B
16
CASE 948F
DT SUFFIX
TSSOP-16
D SUFFIX
SOIC-16
ORDERING INFORMATION
1
1
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A
WL, L
Y
W, WW = Work Week
G or G
http://onsemi.com
= Wafer Lot
= Device Code
= Assembly Location
= Year
= Pb-Free Package
16
Publication Order Number:
1
16
1
DIAGRAMS*
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MARKING
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NB2309A/D

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nb2309a Summary of contents

Page 1

... The NB2309A is available in two different configurations, as shown in the ordering information table. The NB2309A1 is the base part. The NB2309Ax1H* is the high drive version of the -1 and its rise and fall times are much faster than -1 part. Features • ...

Page 2

... Driven 1 1 Driven 1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and the output. NB2309A PLL MUX SELECT INPUT DECODING Figure 1. Block Diagram CLKOUT (Note 1) Clock ...

Page 3

... CLKOUT (Note 3) 2. Weak pulldown. 3. Weak pulldown on all outputs. 4. Weak pullup on these inputs. NB2309A 1 REF NB2309A GND Figure 2. Pin Configuration Description Input reference frequency tolerant input. Buffered clock output, Bank A. Buffered clock output, Bank A. ...

Page 4

... IL I Input HIGH Current IH V Output LOW Voltage OL V Output HIGH Voltage OH I Supply Current (Commercial Temp Supply Current (Industrial Temp REF input has a threshold voltage of V NB2309A Min -0.5 -0.5 -0.5 -65 Description Industrial Test Conditions (-1) ...

Page 5

... Output Slew Rate 8 t Cycle-to-Cycle Jitter J t PLL Lock Time LOCK 6. All parameters specified with loaded outputs and apply to both PLL-Mode and PLL-Bypass Mode. NB2309A (Note 6) Test Conditions 30 pF load 10 pF load (-1, -1H) Measured at 1 66.67 MHz OUT (-1H) < 50 MHz (-1, -1H) Measured between 0 ...

Page 6

... DD OUTPUTS 0 0.1 mF GND GND Figure 8. Test Circuit #1 NB2309A For applications requiring zero input-output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not used, it must have a capacitive load equal to that on other outputs, for obtaining zero-input-output delay. SWITCHING WAVEFORMS 2.0 V 0.8 V OUTPUT ...

Page 7

... NB2309AI1DR2G 2309AI1G NB2309AI1HDG 2309AI1HG NB2309AI1HDR2G 2309AI1HG NB2309AI1DTG 2309AI1 NB2309AI1DTR2G 2309AI1 NB2309AI1HDTG 2309AI1H NB2309AI1HDTR2G 2309AI1H †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NB2309A Operating Range Package Industrial ...

Page 8

... -V- C 0.10 (0.004) -T- SEATING D PLANE 16X 0.36 *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. NB2309A PACKAGE DIMENSIONS TSSOP-16 CASE 948F-01 ISSUE Ç Ç Ç 9 É É É ...

Page 9

... D 0.35 0.49 0.014 0.019 F F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019 1.27 PITCH ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB2309A/D ...

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