P80C562 Philips Semiconductors, P80C562 Datasheet
P80C562
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P80C562 Summary of contents
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... DATA SHEET P83C562; P80C562 8-bit microcontroller Product specification File under Integrated Circuits, IC20 INTEGRATED CIRCUITS 1997 Apr 16 ...
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... T2 Control Register (TM2CON) 12.2.2 Capture Control Register (CTCON) 12.2.3 Interrupt Flag Register (TM2IR) 12.2.4 Set Enable Register (STE) 12.2.5 Reset/Toggle Enable register (RTE) 12.3 Watchdog Timer (T3) 1997 Apr 08 P83C562; P80C562 13 SERIAL I/O 14 INTERRUPT SYSTEM 14.1 Interrupt Vectors 14.2 Interrupt priority 14.3 Interrupt Enable and Priority Registers 14.3.1 Interrupt Enable Register 0 (IEN0) 14 ...
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... Full-duplex UART compatible with the standard 80C51 On-chip Watchdog Timer Oscillator frequency: 3 MHz. 2 GENERAL DESCRIPTION The P80C562/P83C562 (hereafter generally referred to as P8xC562) single-chip 8-bit microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The P8xC562 has the same instruction set as the 80C51. ...
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... Philips Semiconductors 8-bit microcontroller 4 BLOCK DIAGRAM 1997 Apr 08 P83C562; P80C562 4 Product specification pagewidth full handbook, ...
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... STADC 0 1 P8xC562 2 3 PORT PORT RST EW MBH347 Fig.2 Functional diagram. 5 Product specification P83C562; P80C562 alternative function 0 AD0 1 AD1 2 AD2 LOW ORDER 3 AD3 ADDRESS PORT 0 AND 4 AD4 DATA BUS 5 AD5 6 AD6 7 AD7 0 CT0I 1 CT1I ...
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... P4.7/CMT1 15 RST 16 P1.0/CT0I 17 P1.1/CT1I 18 P1.2/CT2I 19 P1.3/CT3I 20 P1.4/T2 21 P1.5/RT2 22 P1.6 23 P1.7 24 P3.0/RXD 25 P3.1/TXD 26 P3.2/INT0 Fig.3 Pinning configuration for PLCC68 (SOT188-2) package. 1997 Apr 08 P83C562; P80C562 P8xC562 6 Product specification REF 59 AV REF 58 57 P0.0/AD0 56 P0.1/AD1 55 P0.2/AD2 54 P0.3/AD3 53 P0.4/AD4 52 P0.5/AD5 51 P0.6/AD6 50 P0.7/AD7 EA ...
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... P3.7: 8-bit quasi-bidirectional I/O port line; RD: External Data Memory Read strobe. n.c. 32, 33 Not connected. XTAL2 34 Crystal Oscillator Output: output of the inverting amplifier that forms the oscillator. Left open-circuit when an external oscillator clock is used. 1997 Apr 08 P83C562; P80C562 DESCRIPTION 7 Product specification + 0 0 ...
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... Ground, analog part. For ADC receiver and reference voltage Power supply, analog part (+5 V). For ADC receiver and reference voltage. DD P5.7/ADC7 62 to 68, P5.7 to P5.0: 8-bit input port lines ADC7 to ADC0: eight analog ADC inputs P5.0/ADC0 1997 Apr 08 P83C562; P80C562 DESCRIPTION 8 Product specification ...
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... If the security bit has been set to a logic 0 there are no restrictions for the MOVC instructions. Table 2 Memory access by the MOVC instruction MOVC INSTRUCTION MOVC in internal program memory MOVC in external program memory 9 Product specification P83C562; P80C562 PROGRAM MEMORY ACCESS INTERNAL EXTERNAL YES YES NO YES ...
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... Boolean variables to provide excellent bit handling. OVERLAPPED SPACE 255 EXTERNAL INDIRECT ONLY ( 127 DIRECT AND INDIRECT 0 0 INTERNAL DATA MEMORY Fig.4 Memory map. 10 Product specification P83C562; P80C562 64K SPECIAL FUNCTION REGISTERS 0 EXTERNAL DATA MEMORY MBC745 ...
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... Fig.5 Special Function Register memory map. 11 Product specification P83C562; P80C562 DIRECT BYTE ADDRESS (HEX) FFH FEH FDH FCH F8 F8H F0H F0 EFH EEH EDH ECH EBH EAH E8 E8H E0 E0H SFRs containing ...
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... P83C562; P80C562 DIRECT BYTE ADDRESS (HEX) B8 B8H B0 B0H AFH AEH ADH ACH ABH AAH A9H A8 A8H A0 A0H SFRs containing directly addressable 99H bits 98 98H 90 90H 8DH 8CH ...
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... INPUT BUFFER 13 Product specification P83C562; P80C562 match between timer counter T2 and its compare registers. Unused analog inputs can be used as digital inputs. As Port 5 lines may be used as inputs to the ADC, these digital inputs have an inherent hysteresis to prevent the input logic from drawing too much current from the power lines when driven by analog signals ...
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... Both PWMn output pins are driven by push-pull drivers, and are not shared with any other function. PMW0 8-BIT COMPARATOR 8-BIT COUNTER PRESCALER PWMP 8-BIT COMPARATOR PWM1 14 Product specification P83C562; P80C562 , at the PWMn outputs is PWM f OSC f = ------------------------------------------------------------ - PWM 2 1 PWMP 255 ...
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... Pulse width ratio LOW/HIGH ratio of PWMn signals 0 PWM1.0 1997 Apr PWMP.5 PWMP.4 PWMP PWM0.5 PWM0.4 PWM0 PWM1.5 PWM1.4 PWM1.3 15 Product specification P83C562; P80C562 PWMP.2 PWMP.1 DESCRIPTION PWM0.2 PWM0.1 DESCRIPTION PWMn = ----------------------------------------- - 255 – PWMn PWM1.2 PWM1.1 ...
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... AADR.0 to AADR.2 in ADCON. 8-BIT ADC INTERNAL BUS Fig.9 Functional diagram of analog input. 16 Product specification P83C562; P80C562 Analog input pins STADC analog reference supply (analog part) ground (analog part ADCH MBH350 ...
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... ADC busy, start of a new conversion is blocked Conversion completed; start of a new conversion is blocked Intermediate status for a maximum of one machine cycle before conversion is completed. 1997 Apr ADEX ADCI ADCS 17 Product specification P83C562; P80C562 2 1 AADR2 AADR1 DESCRIPTION OPERATION 0 AADR0 ...
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... Mode 3 as previously described. 1997 Apr 08 P83C562; P80C562 12.2 Timer T2 Capture and Compare Logic Timer 16-bit timer/counter which has, coupled to it, capture and compare facilities. The operational diagram is shown in Fig ...
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... PRESCALER T2 COUNTER P4.0 P4.1 P4.2 I/O port 4 P4.3 P4.4 P4.5 P4.6 P4.7 T2 SFR address: TML2 = lower 8 bits TMH2 = higher 8 bits Fig.10 Block diagram of Timer T2 configuration. 19 Product specification P83C562; P80C562 CT2I INT CT3I CTI2 CT2 8-bit overflow interrupt 16-bit overflow interrupt COMP COMP INT INT CM0 (S) CM2 (T) CM1 (R) INT ...
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... Timer T2 is halted clock source = 1 0 Test mode; do not use clock source = pin T2 1997 Apr 08 (TM2CON T2ER T2B0 T2P1 clock source clock source clock source OSC 20 Product specification P83C562; P80C562 T2P0 T2MS1 DESCRIPTION T2 CLOCK MODE 0 T2MS0 ...
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... Interrupt Enable Register 1 (IEN1) is used to enable/disable Timer 2 interrupts. 2. Interrupt Priority Register 1 (IP1) is used to determine the Timer 2 interrupt priority. 1997 Apr 08 (CTCON CTN2 CTP2 CTN1 (TM2IR CMI1 CMI0 CTI3 21 Product specification P83C562; P80C562 2 1 CTP1 CTN0 DESCRIPTION 2 1 CTI2 CTI1 DESCRIPTION 0 CTP0 0 CTI0 ...
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... If RTE.n is LOW then P4.n is not affected by a match of CM1 and T2 or CM2 and T2. For more information, refer to the 8051-based “8-bit Microcontrollers Data Handbook IC20” . 1997 Apr SP45 SP44 SP43 DESCRIPTION (RTE RP45 RP44 RP43 DESCRIPTION 22 Product specification P83C562; P80C562 SP42 SP41 SP40 RP42 RP41 RP40 ...
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... Watchdog Timer and enables the Power-down mode. INTERNAL BUS PRESCALER TIMER T3 (8-BIT) 11-BIT CLEAR LOAD LOADEN CLEAR WLE PCON.4 INTERNAL BUS Fig.11 Functional diagram of Watchdog Timer. 23 Product specification P83C562; P80C562 V DD overflow P RST internal reset R RST PD LOADEN PCON.1 MBC753 ...
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... Both external interrupts can be programmed to be level-activated or transition-activated; an active LOW level allows 'wire-ORing' of several interrupt sources to the input pin. 1997 Apr 08 P83C562; P80C562 14.1 Interrupt Vectors Table 24 gives the vector address in Program Memory where the appropriate interrupt service routine is located. ...
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... CAPTURE 2 TIMER 2 COMPARE 2 UART T SERIAL PORT R CT3I TIMER 2 CAPTURE 3 TIMER T2 OVERFLOW 1997 Apr 08 interrupt enable registers interrupt priority registers global enable Fig.12 Interrupt system. 25 Product specification P83C562; P80C562 polling hardware high h1 d1 priority i1 interrupt ...
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... Enable T2 capture register 1 interrupt. 0 ECT0 Enable T2 capture register 0 interrupt. Note 1. Logic 0 = interrupt disabled; Logic 1 = interrupt enabled. 1997 Apr 08 0 (IEN0 ES0 ET1 1 (IEN1 ECM1 ECM0 ECT3 26 Product specification P83C562; P80C562 EX1 ET0 DESCRIPTION ECT2 ECT1 DESCRIPTION 0 EX0 0 ECT0 ...
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... PCT0 T2 capture register 0 priority interrupt level. Note 1. A logic 0 = low priority; a logic 1 = high priority. 1997 Apr 08 0 (IP0 PS0 PT1 1 (IP1 PCM1 PCM0 PCT3 27 Product specification P83C562; P80C562 PX1 PT0 DESCRIPTION PCT2 PCT1 DESCRIPTION 0 PX0 0 PCT0 ...
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... Product specification P83C562; P80C562 P - OWER DOWN MODE may be reduced to DD PORT 2 PORT 3 PORT 4 port data port data port data port data port data port data ...
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... If logic 1s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is (0X000000). 1997 Apr 08 XTAL1 OSCILLATOR CLOCK GENERATOR RFI WLE GF1 DESCRIPTION 29 Product specification P83C562; P80C562 interrupts serial ports timer blocks CPU T2 PWM IDL ADC MBC752 2 1 GF0 PD 0 IDL ...
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... RST is HIGH and is repeated every cycle until RST goes LOW. The internal RAM is not affected by reset. When V is turned on, the RAM content is indeterminate internal reset leaves the internal registers as shown in Table 36. 1997 Apr 08 P83C562; P80C562 k, halfpage Use fundamental crystals only. Fig.14 P8xC562P8xC562 oscillator circuit. ...
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... Product specification P83C562; P80C562 Power-on-reset is turned on, and provided its rise-time does not DD via a 2.2 F capacitor. DD minus the capacitor voltage, and DD as the capacitor charges through the ground. The larger the capacitor, RST decreases. V ...
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... Decrement direct byte DEC @Ri Decrement indirect RAM INC DPTR Increment data pointer MUL AB Multiply A DIV AB Divide Decimal adjust A 1997 Apr 08 DESCRIPTION B 32 Product specification P83C562; P80C562 OPCODE BYTES CYCLES (HEX 26 ...
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... Rotate A left RLC A Rotate A left through the carry fl Rotate A right RRC A Rotate A right through the carry flag SWAP A Swap nibbles within A 1997 Apr 08 DESCRIPTION 33 Product specification P83C562; P80C562 OPCODE BYTES CYCLES (HEX 56 ...
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... Pop direct byte from stack XCH A,Rr Exchange register with A XCH A,direct Exchange direct byte with A XCH A,@Ri Exchange indirect RAM with A XCHD A,@Ri Exchange LOW-order nibble indirect RAM with A 1997 Apr 08 DESCRIPTION 34 Product specification P83C562; P80C562 OPCODE BYTES CYCLES (HEX E6 ...
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... Compare immediate to ind. and jump if not equal DJNZ Rr,rel Decrement register and jump if not zero DJNZ direct,rel Decrement direct and jump if not zero NOP No operation 1997 Apr 08 DESCRIPTION 35 Product specification P83C562; P80C562 OPCODE BYTES CYCLES (HEX ...
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... Range is 128 to +127 bytes relative to first byte of the following instruction. Hexadecimal opcode cross-reference * 1997 Apr 08 DESCRIPTION DESCRIPTION 36 Product specification P83C562; P80C562 OPCODE BYTES CYCLES (HEX ...
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First hexadecimal character of opcode AJMP LJMP 0 NOP addr11 addr16 JBC ACALL LCALL 1 bit,rel addr11 addr16 JB AJMP 2 RET bit,rel addr11 JNB ACALL 3 RETI bit,rel addr11 JC AJMP ORL 4 rel addr11 direct,A ...
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... DD(PD) DD(max DD(PD) DD(max DD(PD) DD(max Product specification P83C562; P80C562 MIN. MAX. UNIT 0.5 +6.5 V 5 +150 +125 MHz. OSC MIN. MAX. UNIT 4.5 5 ...
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... A 0. 400 A 2 120 A 0. test frequency = 1 MHz amb 0.2 V 4.5 DDA DD Port DDA DDA(PD) DDA(max) 39 Product specification P83C562; P80C562 MIN. MAX. UNIT 0. 150 5 ...
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... V. The ADC is monotonic with no missing codes. Measurement by 40 Product specification P83C562; P80C562 MIN ...
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... Idle mode 4.5 V. ID(max) DD These values are valid within the specified frequency range. Fig.18 Supply current (I 1997 Apr (mA (1) ( function of frequency at XTAL1 ( P83C562; P80C562 MBC747 ( (MHz) ). osc Product specification ...
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... Centre of a step of the actual transfer curve. 1997 Apr 08 offset error OS e (2) (1) (5) (4) (3) 1 LSB (ideal 250 251 252 253 254 255 256 1 LSB ideal = Fig.19 ADC conversion characteristic. 42 Product specification P83C562; P80C562 gain error (LSB ) ideal IN AV REF AV REF MBH351 1024 ...
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... If f CLK osc 1997 Apr for all other outputs unless specified. See Figs 23 to 25. L PARAMETER = 16 MHz then t osc 43 Product specification P83C562; P80C562 MHz f = VARIABLE OSC OSC MIN. MAX. MIN CLK ...
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... LOAD (b) 0.5 V for a logic 1, and 0.45 V for a logic 0. DD for a logic 1, and V for a logic 0. See Fig.25 (a). IL(max) level occurs (for testing purposes only). See Fig.25 (b Fig.20 AC inputs test conditions. 44 Product specification P83C562; P80C562 MLA753 ...
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... A8 - A15 address inst. address address A8 - A15 old data sampling time of I/O port pins during input (including INT0 and INT1) Fig.21 Instruction cycle timing. 45 Product specification P83C562; P80C562 one machine cycle inst. address inst. ...
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... AFR t AD address A8 to A15 or Port 2 out Fig.23 Read from data memory. 46 Product specification P83C562; P80C562 t PXIZ inst. input t PXIX address A8 to A15 t WHLH DFR t DR data input MGA176 MBC743 ...
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... LL ALE PSEN PORT 0 PORT 2 1997 Apr DWX address A8 to A15 or special function registers (SFR) Fig.24 Write to data memory. 47 Product specification P83C562; P80C562 t WHLH data output t WD MBC744 ...
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... Apr 08 PARAMETER t HIGH IH1 V IH1 0.8 V 0 LOW t CK Fig.25 External clock drive XTAL. 16 MHz OSC MIN. 0.75 492 8 Product specification P83C562; P80C562 MIN. MAX. 62.5 285 0.75 3. IH1 V IH1 0.8 V MBC479 VARIABLE OSCILLATOR MAX. MIN. MAX. 12t ...
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... scale (1) ( 0.81 24.33 24.33 23.62 23.62 1.27 0.66 24.13 24.13 22.61 22.61 0.032 0.958 0.958 0.930 0.930 0.05 0.026 0.950 0.950 0.890 0.890 REFERENCES JEDEC EIAJ MO-047AC 49 P83C562; P80C562 detail max. 25.27 25.27 1.22 1.44 0.51 0.18 0.18 25.02 25.02 1.07 1.02 0.995 ...
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... C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes 1997 Apr 08 P83C562; P80C562 23.3 Wave soldering Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used ...
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... Philips customers using or selling these products for use in such applications their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1997 Apr 08 P83C562; P80C562 51 Product specification ...
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... Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel ...