TS68020 ATMEL Corporation, TS68020 Datasheet
TS68020
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TS68020 Summary of contents
Page 1
... Power Supply: 5.0 V ± 10% DC Description The TS68020 is the first full 32-bit implementation of the TS68000 family of micropro- cessors. Using HCMOS technology, the TS68020 is implemented with 32-bit registers and data paths, 32-bit addresses, a rich instruction set, and versatile addressing modes. Screening/Quality This product is manufactured in full compliance with either: • ...
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... Figure block diagram of the TS68020. The processor can be divided into two main sections: the bus controller and the micromachine. This division reflects the autonomy with which the sections operate ...
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... Programmed logical arrays (PLAs) are used to provide instruction decode and sequenc- ing information. The instruction pipe and other individual control sections provide the secondary decode of instructions and generated the actual control signals that result in the decoding and interpretation of nanorom and micorom information. Figure 2. PGA Terminal Designation Figure 3. CQFP Terminal Designation TS68020 3 ...
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... Figure 4. Functional Signal Groups Signal Description Group Address Bus Data Bus Logic Clock TS68020 4 Figure 4 illustrates the functional signal groups and Table 1 lists the signals and their function. The V and GND pins are separated into four groups to provide individual power sup- CC ply connections for the address bus buffers, data bus buffers, and all other output buffers and internal logic ...
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... Indicates that a Valid Address is on The Bus. Indicates that Valid Data Placed on the Data Bus by an External Device or has been Laced on the Data Bus by the TS68020. Defines the Bus Transfer as an MPU Read or Write. Provides an Enable Signal for External Data Buffers. ...
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... Requirements General Design and Construction Terminal Connections Lead Material and Finish Package TS68020 6 This drawing describes the specific requirements for the microprocessor 68020, 16.67 MHz, 20 MHz and 25 MHz, in compliance with the MIL-STD-883 class B. • MIL-STD-883: Test Methods and Procedures for Electronics • ...
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... Max 5 Sec. Soldering Min 4.5 -0.3 2.4 -55 (1) 68020-16 68020-20 68020-25 68020-16 8 68020-20 12.5 68020-25 12.5 68020-16 60 68020-20 50 68020-25 40 68020-16 24 68020-20 20 68020-25 19 68020-16 24 68020-20 20 68020-25 19 TS68020 Max Unit +7.0 V +7.0 V 2.0 W 1.9 W ° +125 C ° +85 C ° +150 C ° +270 C Max Unit 5.5 V 0.5 V 5.25 V ° +125 C Ω (1) pF ...
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... Thermal Resistance - Ceramic Junction to Case JC Power Considerations TS68020 8 This device contains protective circuitry against damage due to high static voltages or electrical fields; however advised that normal precautions be taken to avoid applica- tion of any voltages higher than maximum-rated voltages to this high-impedance circuit. ...
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... Table 5: Static electrical characteristics for all electrical variants. Table 6: Dynamic electrical characteristics for 68020-16 (16.67 MHz), 68020-20 (20 MHz) and 68020-25 (25 MHz). For static characteristics, test methods refer to “Test Conditions Specific to the Device” on page 14 hereafter of this specification (Table 7). TS68020 ) can be separated into two components, JA (4) is user depen that θ ...
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... Outputs A0-A31, AS, DBEN, DS, D0-D31 R/W, FC0-FC2, RMC, SIZ0-SIZ1 I Output Short-circuit Current OS (Any Output) TS68020 10 For dynamic characteristics (Table 6), test methods refer to IEC 748-2 method, where existing. Indication of “min.” or “max.” in the column “test temperature” means minimum or maxi- mum operating temperature. ...
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... TS68020 = 2.4V (See also Unit Notes (11 ( (11 (11) ns (8) ns (11 (6) ns (6) ns ...
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... Asynchronous Input Setup Time AIST t Asynchronous Input Hold Time AIHT t DSACKx Asserted to BERR/HALT DABA Asserted t Data Out Hold from Clock High DOCH t BERR Negated to HALT Negated BNHN (Rerun) TS68020 12 68020-16 68020-20 Interval Number Min Max Min 27A 20 15 ...
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... HIGH: DSACK0, DSACK1, CDIS, IPL0-IPL2, DBEN, AVEC, BERR. 2115A–HIREL–07/02 68020-16 68020-20 Interval Number Min Max Min 8.0 16.67 12 512 512 TS68020 68020-25 Max Min Max Unit Notes 20.0 12.5 25 MHz (11) 20 (11) 512 Clks (11 (10)(11) 1 Clks (10)(11) 1 Clks 13 ...
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... Note: 1. Equivalent loading may be simulated by the tester. TS68020 14 The applicable loading network shall be defined in column “Test conditions” of Table 6, referring to the loading network number as shown in Figure 6, Figure 7, Figure 8 below. Figure 6. RESET Test Loads Figure 7. HALT Test Load Figure 8. Test Load ...
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... The times specified in Table 6 as dynamic characteristics are defined in Figure 9 below reference number given the column “interval N°” of the tables together with the rel- evant figure number. TS68020 15 ...
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... Timing measurements are referenced to and from a low voltage of 0.8V and a high voltage of 2.0V, unless otherwise noted. The voltage swing thorough this range should start outside and pass through the range such that the rise or fall will be linear between 0.8V and 2.0V. TS68020 16 2115A–HIREL–07/02 ...
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... Timing measurements are referenced to and from a low voltage of 0.8V and a high voltage of 2.0V, unless otherwise noted. The voltage swing thorough this range should start outside and pass through the range such that the rise or fall will be linear between 0.8V and 2.0V. 2115A–HIREL–07/02 TS68020 17 ...
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... Finally, the measurements for signal-to-signal specification are also shown. Note that the testing levels used to verify conformance of the TS68020 to the AC speci- fications does not affect the guaranteed DC operation of the device as specified in the DC electrical characteristics. ...
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... This input timing is applicable to all parameters specified relative to the falling edge of the clock. 4. This input timing is applicable to all parameters specified relative to the falling edge of the clock. 5. This timing is applicable to all parameters specified relative to the assertion/negation of another signal. 2115A–HIREL–07/02 TS68020 19 ...
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... Additional Information Power Consideration Capacitance (Not for Inspection Purposes Capacitance Derating Curves TS68020 20 Additional information shall not be for any inspection purposes. See Table 4. ) Symbol Parameter Test Conditions Input Capacitance MHz Figure 13 to Figure 18 inclusive show the typical derating conditions which apply. The capacitance includes any stray capacitance ...
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... Figure 14. ECS and OCS Capacitance Derating Curve Figure 15. R/W, FC, SIZ0-SIZ1, and RMC Capacitance Derating Curve TS68020 21 ...
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... TS68020 22 Figure 16. DS, AS, IPEND, and BG Capacitance Derating Curve Figure 17. DBEN Capacitance Derating Curve 2115A–HIREL–07/02 ...
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... All microprocessors of the TS68000 Family support instruction tracing (via the T0 status bit in the TS68020) where each instruction executed is followed by a trap to a user- defined trace routine. The TS68020 adds the capability to trace only the change of flow instructions (branch, jump, subroutine call and return, etc ...
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... Figure 19. User Programming Model TS68020 24 The TS68000 Family processors distinguish address spaces as supervisor / used and program/data. These four combinations are specified by the function code pins (FC0/FC1/FC2) during bus cycles, indication the particular address space. Using the function codes, the memory sub-system can distinguish between authorized access (supervisor mode is privileged access) and unauthorized access (user mode may not have access to supervisor program or data areas) ...
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... In addition, operations on other data types, such as memory addresses, status word data, etc...., are provided in the instruction set. The co-processor mechanism allows direct support of floating-point data type with the TS68881 and TS68882 floating-point co-processors, as well as specialized user-defined data types and functions. TS68020 25 ...
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... The program counter relative mode also has index and offset capabilities; programmers find that this addressing mode is required to support position-independent software. In addition to these addressing modes, the TS68020 provides data operand sizing and scaling; these features provide performance enhancements to the programmer. ...
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... Table 8. TS68020 Addressing Modes (Continued) Addressing Modes Absolute Absolute Short Absolute Long Immediate Notes Data Register, D0-D7 Address Register, A0-A7 twos-complement, or sign—extended displacement; added as part of the effective calculation; size bits; when omitted assemblers use a value of zero. ...
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... Instruction Set Overview TS68020 28 The TS68020 instruction set is shown in Table 9. Special emphasis has been given to the instruction set’s support of structured high-level languages and sophisticated operat- ing systems. Each instruction, with few exceptions, operates on bytes, words, and long words and most instructions can use any of the 18 addressing modes. Many instruction extensions have been made on the TS68020 to take advantage of the full 32-bit opera- tion where, on the earlier 68000 Family members, only 8 and 16 bits values were used ...
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... Move Condition Code Register Move Status Register Move User Stack Pointer Move Control Register Move Multiple Registers Move Peripheral Move Quick Move Alternate Address Space Signed Multiply Unsigned Multiply Negate Decimal with Extend Negate Negate with Extend No Operation Logical Complement TS68020 29 ...
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... TS68020 30 Table 9. Instruction Set (Continued) Mnemonic OR ORI PACK PEA RESET ROL, ROR ROXL, ROXR RTD RTE RTM RTR RTS SBCD Scc STOP SUB SUBA SUBI SUBQ SUBX SWAP TAS TRAP TRAPcc TRAPV TST UNLK UNPK Co-processor Instructions cpBCC cpDBcc cpGEN cpRESTORE ...
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... System Traps 2115A–HIREL–07/02 The TS68020 supports variable length bit field operations up to 32-bit. A bit field may start in any bit position and span any address boundary for the full length of the bit field the 32-bit maximum. The bit field insert (BFINS) inserts a value into a field. Bit field extract unsigned (BFEXTU) and bit field extract signed (BFEXTS) extract an unsigned or signed value from the field ...
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... TS68020 to perform the necessary actions to verify legitimate access to modules. The full addressing range of the TS68020 is 4-Gbyte (4, 294, 967, 296). However, most TS68020 systems implement a smaller physical memory. Nonetheless, by using virtual memory techniques, the system can be made to appear to have a full 4-Gbyte of physi- cal memory available to each user program ...
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... This feature allows the programmer the ability to write code that is not bus-width specific. For example, long word (32-bit) accesses to peripherals may be used in the code, yet the TS68020 will transfer only the amount of data that the peripheral can manage. This feature allows the peripheral to define its port size as 8-, 16-, or 32-bit wide and the TS68020 will dynamically size the data transfer accordingly, using multiple bus cycles when necessary ...
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... Adhering to the sequential execution model, the request to the co-processor continues a floating-point operation the co-processor completes each TS68881 and TS68882 instruction before it starts the next, and the TS68020 is allowed to proceed as it can in a concurrent fashion. co-processors are divided into two types by their bus utilization characteristics. A co- processor is a DMA co-processor if it can control the bus independent of the main pro- cessor ...
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... Other microprocessors in the TS68000 Family can operate any TS68000 co-processor even though they may not have the hardware implementation of the co-processor inter- face as does the TS68020. Since the co-processor is operated through the co- processor interface registers which are accessed via normal asynchronous bus cycles, the co-processor may be used as a peripheral device ...
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... Up to eight processors are supported in a single system with a system-unique co-pro- cessor identifier encoded in the co-processor instruction. When accessing a co- processor, the TS68020 executes standard read and write bus cycle in CPU address space, as encoded by the function codes, and places the co-processor identifier on the address bus to be used by chip-select logic to select the particular co-processor ...
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... The main processor “executes” this primitive, thereby providing the services requires by the co-processor. Table 11 summarizes the co-pro- cessor primitives that the TS68020 accepts. Exception can be generated by either internal or external causes. The externally gener- ated exceptions are the interrupts, the bus error, and reset requests. The interrupts are requests from peripheral devices for processor action while the bus error and reset pins are used for access control and processor restart ...
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... ACC the access time of the rest of the system, and h is the hit ratio or the percentage of time that the data is found in the cache. Thus, for a given system design, an TS68020 on- chip cache provides a substantial CPU performance increase, or allows much slower and less expensive memories to be used for the same processor performance. ...
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... FC2 (user/supervisor) value, one valid bit, and 32-bit of instruction data (Figure 22). The TS68020 employs a 32-bit data bus and fetches instructions on long word address boundaries. Hence, each 32-bit instruction fetch brings in two 16-bit instruction words which are then written into the on-chip cache. When the cache is enabled, the subse- quent prefetch will find the next 16-bit instruction word is already present in the cache and the related bus cycle is saved ...
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... Preparation for Delivery Certificate of Compliance Handling TS68020 40 Atmel offers a certificate of compliance with each shipment of parts, affirming the prod- ucts are in compliance with MIL-STD-883 and guaranteeing the parameters are tested at extreme temperatures for the entire temperature range. MOS devices must be handled with certain precautions to avoid damage due to accu- mulation of static charge ...
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... Package Mechanical Data Figure 23. 114-lead - Ceramic Pin Grid Array Figure 24. 132 Pins - Ceramic Quad Flat Pack 2115A–HIREL–07/02 TS68020 41 ...
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... Mass Terminal Connections 114-lead - Ceramic Pin Grid Array 132-lead - Ceramic Quad Flat Pack TS68020 42 PGA 114 - 6 grams typically CQFP 132 - 14 grams typically See Figure 2. See Figure 3. 2115A–HIREL–07/02 ...
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... TS68020MFB/C20 MIL-STD-883 TS68020MF1B/C20 MIL-STD-883 TS68020MFB/C25 MIL-STD-883 TS68020MF1B/C25 MIL-STD-883 TS68020DESC02XA TS68020DESC03XA TS68020DESC04XA TS68020DESC02XC TS68020DESC03XC TS68020DESC04XC TS68020DESC02YA TS68020DESC03YA TS68020DESC04YA TS68020DESC02YC TS68020DESC03YC TS68020DESC04YC Standard Product Commercial Atmel Part-Number TS68020VR16 TS68020VR20 TS68020VR25 TS68020MR16 TS68020MR20 TS68020MR25 2115A–HIREL–07/02 Temperature Range Package PGA 114 PGA 114/tin ...
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... Standard Product Commercial Atmel Part-Number TS68020VF16 TS68020VF120 TS68020VF25 TS68020MF16 TS68020MF20 TS68020MF25 Device Type Temperature range M: -55, +125°C V: -40, +85 Package R = Pin grid array 114 F = CQFP 132 Note: For availability of the different versions, contact your Atmel sales office. TS68020 44 Norms Package Internal Standard ...
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... Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...