ZY7120L-T2 POWER ONE, ZY7120L-T2 Datasheet
ZY7120L-T2
Specifications of ZY7120L-T2
Related parts for ZY7120L-T2
ZY7120L-T2 Summary of contents
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Applications Low voltage, high density systems with Intermediate Bus Architectures (IBA) Point-of-load regulators for high performance DSP, FPGA, ASIC, and microprocessor applications Desktops, servers, and portable computing Broadband, networking, optical, and communications systems Active memory ...
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Reference Documents: ZM7XXX Digital Power Manager. Data Sheet ZM7XXX Digital Power Manager. Programming Manual ® Z-One Graphical User Interface 2 ZM00056-KIT USB Adapter Kit. User Manual 1. Ordering Information Output ...
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Electrical Specifications Specifications apply at the input voltage from 3V to 13.2V, output load from 0 to 20A, ambient temperature from - 40°C to 85°C, 100F output capacitance, and default performance parameters settings unless otherwise noted. 4.1 Input Specifications ...
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Figure 1. Output Voltage as a Function of Input Voltage and Output Current 4.3 Protection Specifications Parameter Type Threshold Threshold Accuracy Type Threshold Programmable in 10% steps Threshold Accuracy From instant when threshold is exceeded until Delay the turn-off command ...
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Type Threshold Threshold Accuracy From instant when threshold is exceeded until Delay the turn-off command is generated Type Turn Off Threshold Temperature is decreasing after the module was Turn On Threshold Threshold Accuracy From instant when threshold is exceeded until ...
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Feature Specifications Parameter Type Maximum Number of Modules Connected in Parallel Maximum Number of Modules Connected in Parallel Current Share Accuracy Interleave (Phase Shift) Turn ON Delay Turn OFF Delay Turn ON Slew Rate Turn OFF Slew Rate Load ...
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Signal Specifications Parameter VDD ViL_sd ViH_sd Vhyst_sd Hysteresis of input Schmitt trigger VoL LOW level sink current @ 0.5V Tr_sd Maximum allowed rise time 10/90%VDD Cnode_sd Ipu_sd Pull-up current source at Vsd=0V Freq_sd Clock frequency of external SD line ...
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Typical Performance Characteristics 5.1 Efficiency Curves Vout=0.5V Vout=1. Output Current, A Figure 2. Efficiency vs. Load. Vin=3.3V, Fsw=500kHz 96 ...
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Vout=0.5V Vout=1. Input Voltage, V Figure 6. Efficiency vs. Input Voltage. Iout=20A, Fsw=500kHz Fsw=500kHz Fsw=750kHz ...
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Vin=3.3V, Vout=2. Vin=5V, Vout=1.2V 87 Vin=12V, Vout= 500 750 Switching Frequency, kHz Figure 10. Efficiency vs. Switching Frequency. Iout=20A 5.2 Turn-On Characteristics Figure 11. Tracking Turn-On. Rising Slew ...
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Figure 14. Turn On with Sequencing and Tracking. Rising Slew Rate Programmed at 0.2V/ms, V1 and V3 delays are programmed at 20ms. Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3 Figure 15. Turn On into Prebiased Load. V3 ...
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Transient Response The pictures below show the deviation of the output voltage in response to the 50-100-50% step load at 1A/μs. In all tests the ZY7120 converters were switching at 1MHz and had 5x22μF and 5x47μF ceramic capacitors connected ...
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Thermal Derating Curves LFM 100 LFM Figure 23. Thermal Derating Curves. Vin=13.2V, Vout=5.0V, Fsw=500kHz LFM 100 LFM Figure 24. Thermal ...
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Typical Application SD 2 DPM I C OK_C OK_B OK_A ZY7120 ADDR Figure 25. Block Diagram of Typical Multiple Output Application with Digital Power Manager and I The block diagram of a typical application of ZY7120 point-of-load converters (POL) ...
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Figure 26. Complete Schematic of the Application Shown in Figure 25. Intermediate Bus Voltage is from 4.75V to 13.2V. ZD-00194 Rev. 2.5, 01-Jul-10 ZY7120 20A DC-DC Intelligent POL Data Sheet 3V to 13.2V Input www.power-one.com 0.5V to 5.5V Output ...
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Pin Assignments and Description Pin Pin Pin Buffer Name Number Type Type VLDO VREF I ...
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Programmable Features Performance parameters of ZY7120 POL converters can be programmed via the industry standard I communication bus without components or rewiring PCB parameter has a default value stored in the volatile memory registers detailed in Table 1. registers ...
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Output Voltage Setpoint The output voltage programming range is from 0.5V to 5.5V. Within this range, there are 256 predefined voltage setpoints. To improve resolution of the output voltage settings, the voltage range is divided into three sub-ranges as ...
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Figure 31. Transient Response with Optimal Voltage Positioning 8.2 Sequencing and Tracking Turn-on delay, turn-off delay, and rising and falling output voltage slew rates can be programmed in the GUI Sequencing/Tracking window shown in Figure directly via ...
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If the falling slew rate control is not utilized, the turn- off delay only determines an interval from the application of the Turn-Off command until both high side and low side switches are turned off. In this case, the output ...
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R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 LR2 LR1 LR0 TCE CLS2 CLS3 Bit 7 Bit 7:5 LR[2:0], Load regulation configuration 000: 0 V/A/Ohm 001: 0.39 V/A/Ohm 010: 0.78 V/A/Ohm 011: 1.18 V/A/Ohm 100: 1.57 V/A/Ohm 101: 1.96 V/A/Ohm 110: 2.35 ...
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All protections can be classified into three groups based on their effect on system operation: warnings, faults, and errors. 8.3.1 Warnings This group includes Overtemperature Warning and Power Good Signal. The warnings do not turn off POLs but rather generate ...
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Tracking Protection Tracking protection is active only when the output voltage is ramping up. The purpose of the protection is to ensure that the voltage differential between multiple rails being tracked does not exceed 250mV. This protection eliminates the ...
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Grouping of POLs Z-Series POLs can be arranged in several groups to simplify fault management. A group of POLs is defined as a number of POLs with interconnected OK pins. A group can include from POLs. ...
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The POL powering the output V1 (Ch3 in the picture) executes the regular turn-off. Since both V1 and V3 have the same delay and slew rate settings they will continue to turn off and on synchronously every 130ms as shown ...
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PWM Parameters Z-Series POLs utilize the digital PWM controller. The controller enables users to program most of the PWM performance parameters, such as switching frequency, interleave, duty cycle, and feedback loop compensation. 8.4.1 Switching Frequency The switching frequency can ...
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Figure 50 shows the input voltage noise of the three- output system with programmed interleave. Instead of all three POLs switching at the same time as in the previous example, the POLs V1, V2, and V3 switch at 67.5°, 180°, ...
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R/W-1 R/W-1 R/W-1 R/W-0 R/W-1 R/W-0 DCL5 DCL4 DCL3 DCL2 DCL1 DCL0 Bit Readable bit Bit 7:2 DCL[5:0], Duty Cycle Limitation W = Writable bit 00h Unimplemented bit, 01h: 1/64 … ...
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The digital signal transmitted over the CS line sets output currents of all POLs to the same level. When POLs are connected in parallel, they must be included in the same parallel bus in the GUI System Configuration window ...
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ZD-00194 Rev. 2.5, 01-Jul-10 ZY7120 20A DC-DC Intelligent POL Data Sheet 3V to 13.2V Input Figure 55. GUI System Configuration Window www.power-one.com 0.5V to 5.5V Output Page ...
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Safety The ZY7120 POL converters do not provide isolation from input to output. The input devices powering ZY7120 must provide relevant isolation requirements according to all IEC60950 based standards. Nevertheless, if the system using the converter needs to receive ...
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The fuse must not be placed in the grounded input line. Abnormal and component failure conducted with the ...
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Mechanical Drawings 13.4 14±0.3 1.27 0.4 0.6 (x10) (x20) 2.03 9.75 12 3.5 8.25±0.3 3.25 Pin 1 15.75 ZD-00194 Rev. 2.5, 01-Jul-10 ZY7120 20A DC-DC Intelligent POL Data Sheet 3V to 13.2V Input All Dimensions are in mm Tolerances: ...
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Unexposed thermal copper area associated with each pad must be free from other traces 1.8 (x 22) 2 0.8 Figure 61. Recommended PCB Layout for Multilayer PCBs Notes: 1. NUCLEAR AND MEDICAL APPLICATIONS - Power-One ...