PIC16F526-I/SL Microchip Technology, PIC16F526-I/SL Datasheet - Page 49
PIC16F526-I/SL
Manufacturer Part Number
PIC16F526-I/SL
Description
IC PIC MCU FLASH 1KX12 14SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F526-ISL.pdf
(122 pages)
2.PIC16F526-ISL.pdf
(22 pages)
3.PIC16F526-IP.pdf
(104 pages)
Specifications of PIC16F526-I/SL
Core Size
8-Bit
Program Memory Size
1.5KB (1K x 12)
Core Processor
PIC
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
11
Program Memory Type
FLASH
Ram Size
67 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 3x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Controller Family/series
PIC16F
No. Of I/o's
12
Eeprom Memory Size
64Byte
Ram Memory Size
67Byte
Cpu Speed
20MHz
No. Of Timers
1
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
67 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 3 Channel
A/d Bit Size
8 bit
A/d Channels Available
3
Height
1.25 mm
Length
8.65 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
3.9 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ICE2000 - EMULATOR MPLAB-ICE 2000 POD
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F526-I/SL
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
8.5
On the PIC16F526 device, the DRT runs any time the
device is powered up. DRT runs from Reset and varies
based on oscillator selection and Reset type (see
Table 8-5).
The DRT operates on an internal RC oscillator. The
processor is kept in Reset as long as the DRT is active.
The DRT delay allows V
for the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic resona-
tors require a certain time after power-up to establish a
stable oscillation. The on-chip DRT keeps the device in
a Reset condition after MCLR has reached a logic high
(V
MCLR and using an external RC network connected to
the MCLR input is not required in most cases. This
allows savings in cost-sensitive and/or space restricted
applications, as well as allowing the use of the
RB3/MCLR/V
The Device Reset Time delays will vary from
chip-to-chip due to V
ation. See AC parameters for details.
The DRT will also be triggered upon a Watchdog Timer
time-out from Sleep. This is particularly important for
applications using the WDT to wake from Sleep mode
automatically.
Reset sources are POR, MCLR, WDT time-out and
wake-up on pin change. See Section 8.8.2 “Wake-up
from Sleep”, Notes 1, 2 and 3.
8.6
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator, which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the RB5/OSC1/CLKIN pin and
the internal 4/8 MHz oscillator. This means that the
WDT will run even if the main processor clock has been
stopped, for example, by execution of a SLEEP instruc-
tion. During normal operation or Sleep, a WDT Reset or
wake-up Reset, generates a device Reset.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer Reset.
The WDT can be permanently disabled by program-
ming the configuration WDTE as a ‘0’ (see Section 8.1
“Configuration Bits”). Refer to the PIC16F526 Pro-
gramming Specifications to determine how to access
the Configuration Word.
© 2007 Microchip Technology Inc.
IH
MCLR) level. Programming RB3/MCLR/V
Device Reset Timer (DRT)
Watchdog Timer (WDT)
PP
pin as a general purpose input.
DD
, temperature and process vari-
DD
to rise above V
DD
min. and
PP
Preliminary
as
TABLE 8-5:
8.6.1
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by
writing to the OPTION register. Thus, a time-out period
of a nominal 2.3 seconds can be realized. These peri-
ods vary with temperature, V
cess variations (see DC specs).
Under worst-case conditions (V
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
8.6.2
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device Reset.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum Sleep time before a WDT wake-up Reset.
HS, XT, LP
EC
INTOSC, EXTRC
Configuration
Oscillator
WDT PERIOD
WDT PROGRAMMING
CONSIDERATIONS
TYPICAL DRT PERIODS
POR Reset
1.125 ms
1.125 ms
18 ms
PIC16F526
DD
DD
and part-to-part pro-
= Min., Temperature
DS41326A-page 47
Subsequent
Resets
18 ms
10 μs
10 μs