PIC16F722-I/SS Microchip Technology, PIC16F722-I/SS Datasheet - Page 194
![IC PIC MCU FLASH 2KX14 28-SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC16F722-I/SS
Manufacturer Part Number
PIC16F722-I/SS
Description
IC PIC MCU FLASH 2KX14 28-SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.AC164112.pdf
(302 pages)
2.PIC16F722-ISS.pdf
(8 pages)
3.PIC16F722-ISS.pdf
(10 pages)
4.PIC16F722-ISS.pdf
(32 pages)
5.PIC16F722-ISS.pdf
(2 pages)
6.PIC16F722-ISS.pdf
(8 pages)
7.PIC16LF724-EP.pdf
(266 pages)
Specifications of PIC16F722-I/SS
Program Memory Type
FLASH
Program Memory Size
3.5KB (2K x 14)
Package / Case
28-SSOP
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
I2C/SCI/SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
25
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 8-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164307 - MODULE SKT FOR PM3 28SSOP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F722-I/SS
Manufacturer:
MICROCHI
Quantity:
60
Part Number:
PIC16F722-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- AC164112 PDF datasheet
- PIC16F722-ISS PDF datasheet #2
- PIC16F722-ISS PDF datasheet #3
- PIC16F722-ISS PDF datasheet #4
- PIC16F722-ISS PDF datasheet #5
- PIC16F722-ISS PDF datasheet #6
- PIC16LF724-EP PDF datasheet #7
- Current page: 194 of 302
- Download datasheet (5Mb)
PIC16F72X/PIC16LF72X
19.2
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
• If the interrupt occurs during or after the
FIGURE 19-1:
TABLE 19-1:
DS41341E-page 194
Name
IOCB
INTCON
PIE1
PIE2
PIR1
PIR2
Legend:
Instruction Flow
(INTCON reg.)
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
execution of a SLEEP instruction, the device will
immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT prescaler
and postscaler (if enabled) will be cleared, the TO
bit will be set and the PD bit will be cleared.
(INTCON reg.)
Note
INTF flag
GIE bit
Instruction
Fetched
Instruction
Executed
OSC1
CLKOUT
INT pin
1:
2:
3:
4:
Wake-up Using Interrupts
PC
(1)
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode.
XT, HS or LP Oscillator mode assumed.
T
GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.
CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
TMR1GIE
TMR1GIF
(4)
OST
IOCB7
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Inst(PC) = Sleep
Bit 7
GIE
—
—
Inst(PC - 1)
= 1024 T
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
PC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
IOCB6
OSC
Bit 6
PEIE
ADIE
ADIF
—
—
(drawing not to scale). This delay does not apply to EC and RC Oscillator modes.
Inst(PC + 1)
Sleep
PC + 1
IOCB5
Bit 5
RCIE
RCIF
T0IE
—
—
Processor in
IOCB4
Bit 4
INTE
TXIE
TXIF
Sleep
—
—
PC + 2
IOCB3
SSPIE
SSPIF
T
Bit 3
RBIE
OST (2)
—
—
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Interrupt Latency
CCP1IE
CCP1IF
Inst(PC + 2)
Inst(PC + 1)
IOCB2
Bit 2
T0IF
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes.
To determine whether a SLEEP instruction executed,
test the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction
should be executed before a SLEEP instruction.
—
—
PC + 2
TMR2IE
TMR2IF
IOCB1
Bit 1
INTF
—
—
(3)
Dummy Cycle
PC + 2
TMR1IE
CCP2IE
TMR1IF
CCP2IF
IOCB0
Bit 0
RBIF
© 2009 Microchip Technology Inc.
Dummy Cycle
Inst(0004h)
POR, BOR
0000 0000
0000 0000
0000 0000
---- ---0
0000 0000
---- ---0
0004h
Value on
Inst(0005h)
Inst(0004h)
other Resets
Value on all
0005h
0000 0000
0000 0000
0000 0000
---- ---0
0000 0000
---- ---0
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