PIC16F684-I/SL Microchip Technology, PIC16F684-I/SL Datasheet - Page 108
![IC PIC MCU FLASH 2KX14 14SOIC](/photos/6/59/65933/150-14-soic_sml.jpg)
PIC16F684-I/SL
Manufacturer Part Number
PIC16F684-I/SL
Description
IC PIC MCU FLASH 2KX14 14SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F684-ISL.pdf
(4 pages)
4.PIC16F684-ISL.pdf
(192 pages)
5.PIC16F684-ISL.pdf
(6 pages)
6.PIC16F684-IST.pdf
(164 pages)
Specifications of PIC16F684-I/SL
Program Memory Type
FLASH
Program Memory Size
3.5KB (2K x 14)
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
14SOIC N
Device Core
PIC
Family Name
PIC16
Maximum Speed
20 MHz
Data Rom Size
256 B
Height
1.25 mm
Length
8.65 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
3.9 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
PIC16F684-I/SLG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F684-I/SL
Manufacturer:
MXIC
Quantity:
1 500
Company:
Part Number:
PIC16F684-I/SL
Manufacturer:
Microchip Technology
Quantity:
32 570
Part Number:
PIC16F684-I/SL
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC16F684
12.4
The PIC16F684 has 11 sources of interrupt:
• External Interrupt RA2/INT
• Timer0 Overflow Interrupt
• PORTA Change Interrupts
• 2 Comparator Interrupts
• A/D Interrupt
• Timer1 Overflow Interrupt
• Timer2 Match Interrupt
• EEPROM Data Write Interrupt
• Fail-Safe Clock Monitor Interrupt
• Enhanced CCP Interrupt
The Interrupt Control register (INTCON) and Peripheral
Interrupt Request Register 1 (PIR1) record individual
interrupt requests in flag bits. The INTCON register
also has individual and global interrupt enable bits.
The Global Interrupt Enable bit, GIE of the INTCON
register, enables (if set) all unmasked interrupts, or
disables (if cleared) all interrupts. Individual interrupts
can be disabled through their corresponding enable
bits in the INTCON register and PIE1 register. GIE is
cleared on Reset.
When an interrupt is serviced, the following actions
occur automatically:
• The GIE is cleared to disable any further interrupt.
• The return address is pushed onto the stack.
• The PC is loaded with 0004h.
The Return from Interrupt instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables unmasked interrupts.
The following interrupt flags are contained in the
INTCON register:
• INT Pin Interrupt
• PORTA Change Interrupt
• Timer0 Overflow Interrupt
The peripheral interrupt flags are contained in the PIR1
register. The corresponding interrupt enable bit is
contained in the PIE1 register.
The following interrupt flags are contained in the PIR1
register:
• EEPROM Data Write Interrupt
• A/D Interrupt
• 2 Comparator Interrupts
• Timer1 Overflow Interrupt
• Timer2 Match Interrupt
• Fail-Safe Clock Monitor Interrupt
• Enhanced CCP Interrupt
DS41202F-page 106
Interrupts
For external interrupt events, such as the INT pin or
PORTA change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
Figure 12-8). The latency is the same for one or
two-cycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
For
comparators, ADC, data EEPROM or Enhanced CCP
modules, refer to the respective peripheral section.
12.4.1
The external interrupt on the RA2/INT pin is
edge-triggered; either on the rising edge if the INTEDG
bit of the OPTION register is set, or the falling edge, if
the INTEDG bit is clear. When a valid edge appears on
the RA2/INT pin, the INTF bit of the INTCON register is
set. This interrupt can be disabled by clearing the INTE
control bit of the INTCON register. The INTF bit must
be cleared by software in the Interrupt Service Routine
before re-enabling this interrupt. The RA2/INT interrupt
can wake-up the processor from Sleep, if the INTE bit
was set prior to going into Sleep. See Section 12.7
“Power-Down Mode (Sleep)” for details on Sleep and
Figure 12-10 for timing of wake-up from Sleep through
RA2/INT interrupt.
Note:
Note 1: Individual interrupt flag bits are set,
additional
2: When an instruction that clears the GIE
RA2/INT INTERRUPT
The ANSEL and CMCON0 registers must
be initialized to configure an analog
channel as a digital input. Pins configured
as analog inputs will read ‘0’ and cannot
generate an interrupt.
regardless
corresponding mask bit or the GIE bit.
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts, which were
ignored, are still pending to be serviced
when the GIE bit is set again.
information
© 2007 Microchip Technology Inc.
of
the
on
status
Timer1,
of
Timer2,
their