ATTINY13A-SSU Atmel, ATTINY13A-SSU Datasheet - Page 94

• Manufacturer Part Number: ATTINY13A-SSU
• Description: IC MCU AVR 1K FLASH 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY13A-SSU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (512 x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SPI
• Total Internal Ram Size: 64Byte
• # I/os (max): 6
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 4-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC
• Package: 8SOIC
• Family Name: ATtiny
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 6
• Number Of Timers: 1
• Processor Series: ATTINY1x
• Core: AVR8
• Data Ram Size: 64 B
• Maximum Clock Frequency: 20 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAKSTK511
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / Rohs Status: Compliant

14.12.3
14.12.3.1
14.12.3.2
94
ATtiny13A
ADCL and ADCH – The ADC Data Register
ADLAR = 0
ADLAR = 1
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter-
rupt is activated.
• Bits 2:0 – ADPS[2:0]: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the input clock
to the ADC.
Table 14-4.
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
Bit
0x05
0x04
Read/Write
Initial Value
Bit
0x05
0x04
Read/Write
Initial Value
ADPS2
0
0
0
0
1
1
1
1
ADC Prescaler Selections
ADC7
ADC9
ADC1
15
15
–
7
R
R
0
0
7
R
R
0
0
ADC6
ADC8
ADC0
14
14
R
R
R
R
ADPS1
–
6
0
0
6
0
0
0
0
1
1
0
0
1
1
ADC5
ADC7
13
13
R
R
R
R
–
5
0
0
–
5
0
0
ADC4
ADC6
12
12
R
R
R
R
–
4
0
0
–
4
0
0
ADPS0
0
1
0
1
0
1
0
1
ADC3
ADC5
11
11
R
R
R
R
–
3
0
0
–
3
0
0
ADC2
ADC4
10
10
–
2
R
R
0
0
–
2
R
R
0
0
ADC9
ADC1
ADC3
Division Factor
R
R
R
R
9
1
0
0
9
–
1
0
0
128
16
32
64
2
2
4
8
ADC8
ADC0
ADC2
R
R
R
R
8
0
0
0
8
–
0
0
0
8126E–AVR–07/10
ADCH
ADCL
ADCH
ADCL