PIC16F688-I/SL Microchip Technology, PIC16F688-I/SL Datasheet - Page 135
![IC PIC MCU FLASH 4KX14 14SOIC](/photos/6/59/65933/150-14-soic_sml.jpg)
PIC16F688-I/SL
Manufacturer Part Number
PIC16F688-I/SL
Description
IC PIC MCU FLASH 4KX14 14SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(204 pages)
3.PIC16F688T-ISL.pdf
(6 pages)
4.PIC16F688T-ISL.pdf
(4 pages)
5.PIC16F688T-ISL.pdf
(688 pages)
6.PIC16F688-EP.pdf
(174 pages)
Specifications of PIC16F688-I/SL
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
12
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SCI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
1
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT14SO-1 - SOCKET TRANSITION 14SOIC 150/208AC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F688T-ISL PDF datasheet #3
- PIC16F688T-ISL PDF datasheet #4
- PIC16F688T-ISL PDF datasheet #5
- PIC16F688-EP PDF datasheet #6
- Current page: 135 of 688
- Download datasheet (3Mb)
1997 Microchip Technology Inc.
Example 8-3
RAM only in Bank0 (such as the PIC16C620). The Bank must be tested before saving any of the
user registers. , W_TEMP, must be defined across all banks and must be defined at the same
offset from the bank base address. The user register, STATUS_TEMP, must be defined in Bank0.
The steps of
1.
2.
3.
4.
5.
6.
If additional locations need to be saved before executing the Interrupt Service Routine (ISR)
code, they should be saved after the STATUS register is saved (step 2), and restored before the
STATUS register is restored (step 4).
Example 8-3: Saving the STATUS and W Registers in RAM
Push
RP0CLEAR
;
ISR_Code
;
Pop
Restore_WREG
Test current bank.
Stores the W register regardless of current bank.
Stores the STATUS register in Bank0.
Executes the Interrupt Service Routine (ISR) code.
Restores the STATUS (and bank select bit register).
Restores the W register.
BTFSS
GOTO
BCF
MOVWF
SWAPF
MOVWF
BSF
GOTO
MOVWF
SWAPF
MOVWF
:
: (Interrupt Service Routine (ISR) )
:
SWAPF
MOVWF
BTFSS
GOTO
BCF
SWAPF
SWAPF
BSF
RETFIE
SWAPF
SWAPF
RETFIE
Example
stores and restores the STATUS and W registers for devices with general purpose
(for Devices with General Purpose RAM Only in Bank0)
STATUS, RP0
RP0CLEAR
STATUS, RP0
W_TEMP
STATUS, W
STATUS_TEMP
STATUS_TEMP, 1
ISR_Code
W_TEMP
STATUS, W
STATUS_TEMP
STATUS_TEMP, W
STATUS
STATUS, RP0
Restore_WREG
STATUS, RP0
W_TEMP, F
W_TEMP, W
STATUS, RP0
W_TEMP, F
W_TEMP, W
8-3:
Section 8. Interrupts
; In Bank 0?
; YES,
; NO, Force to Bank 0
; Store W register
; Swap STATUS register and
;
; Set the bit that corresponds to RP0
; Push completed
; Store W register
; Swap STATUS register and
;
; Restore Status register
;
; In Bank 1?
; NO,
; YES, Force Bank 0
; Restore W register
;
; Back to Bank 1
; POP completed
; Restore W register
;
; POP completed
store in STATUS_TEMP
store in STATUS_TEMP
DS31008A-page 8-13
8
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