PIC16F688-I/SL Microchip Technology, PIC16F688-I/SL Datasheet - Page 76

• Manufacturer Part Number: PIC16F688-I/SL
• Description: IC PIC MCU FLASH 4KX14 14SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-I/SL

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT14SO-1 - SOCKET TRANSITION 14SOIC 150/208AC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F688
9.1.4
To read a program memory location, the user must
write two bytes of the address to the EEADR and
EEADRH registers, set the EEPGD control bit
(EECON1<7>),
(EECON1<0>). Once the read control bit is set, the
program memory Flash controller will use the second
instruction cycle to read the data. This causes the
second instruction immediately following the “
EECON1,RD
available in the very next cycle, in the EEDAT and
EEDATH registers; therefore, it can be read as two
bytes in the following instructions.
EXAMPLE 9-3:
DS41203B-page 74
;
;
NOP
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
NOP
MOVF
MOVF
”
READING THE FLASH PROGRAM
MEMORY
instruction to be ignored. The data is
STATUS, RP0
STATUS, RP1
MS_PROG_EE_ADDR
EEADRH
LS_PROG_EE_ADDR
EEADR
EECON1, EEPGD
EECON1, RD
EEDAT, W
EEDATH, W
and
FLASH PROGRAM READ
then
set
;
; Bank 1
;
; MS Byte of Program Address to read
;
; LS Byte of Program Address to read
; Point to PROGRAM memory
; EE Read
; First instruction after BSF EECON1,RD executes normally
; Any instructions here are ignored as program
; memory is read in second cycle after BSF EECON1,RD
; W = LS Byte of Program EEDAT
; W = MS Byte of Program EEDAT
control
bit
BSF
Preliminary
RD
EEDAT and EEDATH registers will hold this value until
another read or until it is written to by the user (during
a write operation).
Note 1: The two instructions following a program
2: If the WR bit is set when EEPGD = 1, it
memory read are required to be NOP’s.
This prevents the user from executing a
two-cycle
instruction after the RD bit is set.
will be immediately reset to ‘0’ and no
operation will take place.
 2004 Microchip Technology Inc.
instruction
on
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