PIC16F630-I/ST Microchip Technology, PIC16F630-I/ST Datasheet - Page 43

• Manufacturer Part Number: PIC16F630-I/ST
• Description: IC MCU FLASH 1KX14 EEPROM14TSSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F630-I/ST

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP
• Controller Family/series: PIC16F
• No. Of I/o's: 12
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 64Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: RS- 232, USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

6.5
The comparator module also allows the selection of an
internally generated voltage reference for one of the
comparator inputs. The internal reference signal is
used for four of the eight Comparator modes. The
VRCON register, Register 6-2, controls the voltage
reference module shown in Figure 6-5.
6.5.1
The voltage reference can output 32 distinct voltage
levels, 16 in a high range and 16 in a low range.
FIGURE 6-5:
6.6
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output is ensured to have a valid level. If
the internal reference is changed, the maximum delay
of the internal voltage reference must be considered
when using the comparator outputs. Otherwise, the
maximum delay of the comparators should be used
(Table 12-7).
6.7
Both the comparator and voltage reference, if enabled
before entering SLEEP mode, remain active during
SLEEP. This results in higher SLEEP currents than
shown
additional current consumed by the comparator and the
voltage reference is shown separately in the specifica-
tions. To minimize power consumption while in SLEEP
mode, turn off the comparator, CM2:CM0 = 111, and
voltage reference, VRCON<7> = 0.
© 2007 Microchip Technology Inc.
V
DD
Comparator
Comparator Reference
Comparator Response Time
Operation During SLEEP
in
CV
CONFIGURING THE VOLTAGE
REFERENCE
the
REF
VREN
Input
to
power-down
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VR3:VR0
16-1 Analog
8R
specifications.
MUX
R
The
R
16 Stages
The following equations determine the output voltages:
VRR = 1 (low range): CV
VRR = 0 (high range): CV
V
6.5.2
The full range of V
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 6-5) keep CV
V
fore, the CV
V
Voltage Reference can be found in Section 12.0.
While the comparator is enabled during SLEEP, an
interrupt will wake-up the device. If the device wakes
up from SLEEP, the contents of the CMCON and
VRCON registers are not affected.
6.8
A device RESET forces the CMCON and VRCON
registers to their RESET states. This forces the
comparator module to be in the Comparator Reset
mode, CM2:CM0 = 000 and the voltage reference to its
off state. Thus, all potential inputs are analog inputs
with the comparator and voltage reference disabled to
consume the smallest current possible.
DD
DD
DD
. The tested absolute accuracy of the Comparator
. The Voltage Reference is V
/ 32)
R
Effects of a RESET
VOLTAGE REFERENCE
ACCURACY/ERROR
REF
PIC16F630/676
R
output changes with fluctuations in
SS
to V
REF
REF
REF
DD
= (VR3:VR0 / 24) x V
from approaching V
= (V
cannot be realized due to
8R
DD
DD
derived and there-
/ 4) + (VR3:VR0 x
DS40039E-page 41
VRR
DD
SS
or