AT89S52-24PU Atmel, AT89S52-24PU Datasheet

IC MCU 8K FLASH 24MHZ 40-DIP

AT89S52-24PU

Manufacturer Part Number
AT89S52-24PU
Description
IC MCU 8K FLASH 24MHZ 40-DIP
Manufacturer
Atmel
Series
89Sr
Datasheets

Specifications of AT89S52-24PU

Core Processor
8051
Core Size
8-Bit
Speed
24MHz
Connectivity
UART/USART
Peripherals
WDT
Number Of I /o
32
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Package
40PDIP
Device Core
8051
Family Name
89S
Maximum Speed
24 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
32
Interface Type
UART
Number Of Timers
3
Processor Series
AT89x
Core
8051
Data Ram Size
256 B
Maximum Clock Frequency
24 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89ISP
Minimum Operating Temperature
- 40 C
Eeprom Memory
0 Bytes
Input Output
32
Interface
UART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
8K Bytes
Timers
3-16-bit
Voltage, Range
4-5.5 V
Cpu Family
89S
Device Core Size
8b
Frequency (max)
24MHz
Total Internal Ram Size
256Byte
# I/os (max)
32
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
40
Controller Family/series
(8051) 8052
No. Of I/o's
32
Ram Memory Size
256Byte
Cpu Speed
24MHz
No. Of Timers
3
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q2897580

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Features
1. Description
The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K
bytes of in-system programmable Flash memory. The device is manufactured using
Atmel’s high-density nonvolatile memory technology and is compatible with the indus-
try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program
memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-
grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on
a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a
highly-flexible and cost-effective solution to many embedded control applications.
The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes
of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a
six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,
and clock circuitry. In addition, the AT89S52 is designed with static logic for operation
down to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and
interrupt system to continue functioning. The Power-down mode saves the RAM con-
tents but freezes the oscillator, disabling all other chip functions until the next interrupt
or hardware reset.
Compatible with MCS
8K Bytes of In-System Programmable (ISP) Flash Memory
4.0V to 5.5V Operating Range
Fully Static Operation: 0 Hz to 33 MHz
Three-level Program Memory Lock
256 x 8-bit Internal RAM
32 Programmable I/O Lines
Three 16-bit Timer/Counters
Eight Interrupt Sources
Full Duplex UART Serial Channel
Low-power Idle and Power-down Modes
Interrupt Recovery from Power-down Mode
Watchdog Timer
Dual Data Pointer
Power-off Flag
Fast Programming Time
Flexible ISP Programming (Byte and Page Mode)
Green (Pb/Halide-free) Packaging Option
– Endurance: 10,000 Write/Erase Cycles
®
-51 Products
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
AT89S52
1919D–MICRO–6/08

Related parts for AT89S52-24PU

AT89S52-24PU Summary of contents

Page 1

... RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. ...

Page 2

... P1.7 3 RST 4 (RXD) P3 (TXD) P3.1 7 (INT0) P3.2 8 (INT1) P3.3 9 (T0) P3.4 10 (T1) P3.5 11 AT89S52 2 2.3 44-lead PLCC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2 ...

Page 3

... INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PSW PORT 3 LATCH PORT 3 DRIVERS P3.0 - P3.7 P2.0 - P2.7 PORT 2 DRIVERS FLASH LATCH PROGRAM STACK ADDRESS POINTER REGISTER BUFFER PC INCREMENTER PROGRAM COUNTER DUAL DPTR PORT 1 ISP PROGRAM LATCH PORT LOGIC PORT 1 DRIVERS P1.0 - P1.7 AT89S52 3 ...

Page 4

... Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash program- ming and verification. AT89S52 4 ) because of the internal pull-ups. IL Alternate Functions ...

Page 5

... As inputs, Port 3 pins that are externally being pulled low will source current (I Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S52, as shown in the fol- lowing table. Port Pin P3 ...

Page 6

... PSEN Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to exter- nal data memory. ...

Page 7

... Table 5-1. AT89S52 SFR Map and Reset Values 0F8H B 0F0H 00000000 0E8H ACC 0E0H 00000000 0D8H PSW 0D0H 00000000 T2CON T2MOD 0C8H 00000000 XXXXXX00 0C0H IP 0B8H XX000000 P3 0B0H 11111111 IE 0A8H 0X000000 P2 0A0H 11111111 SCON SBUF 98H 00000000 XXXXXXXX P1 90H 11111111 TCON ...

Page 8

... Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0 CP/RL2 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. AT89S52 8 RCLK TCLK ...

Page 9

... Reserved for future expansion DPS Data Pointer Register Select DPS 0 Selects DPTR Registers DP0L, DP0H 1 Selects DPTR Registers DP1L, DP1H 1919D–MICRO–6/08 – – WDIDLE DISRTO – – – – AT89S52 Reset Value = XXX00XX0B – – DISALE Reset Value = XXXXXXX0B – – DPS ...

Page 10

... Data Memory The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. ...

Page 11

... For further information on the UART operation, please click on the document link below: http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF 9. Timer 0 and 1 Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information on the timers’ operation, please click on the document link below: http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF 1919D– ...

Page 12

... Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin. AT89S52 12 Timer 2 Operating Modes CP/RL2 0 ...

Page 13

... C/ TH2 CONTROL TR2 C/ CAPTURE RCAP2H CONTROL EXEN2 – – – shows Timer 2 automatically counting up when DCEN = 0. In this mode, two options AT89S52 TL2 TF2 OVERFLOW RCAP2L TIMER 2 INTERRUPT EXF2 Reset Value = XXXX XX00B – T2OE DCEN Figure 10-2. In this ...

Page 14

... Figure 10-2. Timer 2 Auto Reload Mode (DCEN = 0) ÷12 OSC T2 PIN TRANSITION DETECTOR T2EX PIN Figure 10-3. Timer 2 Auto Reload Mode (DCEN = 1) ÷ OSC PIN AT89S52 14 C/ TH2 CONTR OL TR2 C/ RELO AD RCAP2H CONTROL EXEN2 (DOWN COUNTING RELOAD VALUE) 0FFH 0FFH TH2 ...

Page 15

... The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. 1919D–MICRO–6/08 Timer 2 Overflow Rate Modes 1 and 3 Baud Rates = ----------------------------------------------------------- - Modes 1 and 3 Oscillator Frequency -------------------------------------- - = ------------------------------------------------------------------------------------- - Baud Rate 32 x [65536-RCAP2H,RCAP2L)] Figure AT89S52 Figure 11-1. 16 11-1. This figure is valid only if RCLK or (Table 15 ...

Page 16

... Timer 2 is used as a baud-rate generator possible to use Timer baud-rate gen- erator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L. AT89S52 16 TH2 TL2 ...

Page 17

... DETECTOR P1.1 (T2EX) 13. Interrupts The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE ...

Page 18

... EX1 IE.2 ET0 IE.1 EX0 IE.0 User software should never write 1s to reserved bits, because they may be used in future AT89 products. Figure 13-1. Interrupt Sources AT89S52 18 (LSB) ET2 ES ET1 Function Disables all interrupts interrupt is acknowledged each interrupt source is individually enabled or disabled by setting or clearing its enable bit. ...

Page 19

... Figure 16-1. Oscillator Connections Note: 1919D–MICRO–6/ C1 ± for Crystals = 40 pF ± for Ceramic Resonators AT89S52 Figure 16-1. Either a quartz crystal or Figure 16-2. There are no is restored to CC XTAL2 XTAL1 ...

Page 20

... Table 16-1. Mode Idle Idle Power-down Power-down 17. Program Memory Lock Bits The AT89S52 has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in Table 17- When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. ...

Page 21

... Data Polling: The AT89S52 features Data Polling to indicate the end of a byte write cycle. Dur- ing a write cycle, an attempted read of the last byte written will result in the complement of the written data on P0 ...

Page 22

... XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than 1/16 of the crystal frequency. With a 33 MHz oscillator clock, the maximum SCK frequency is 2 MHz. 20. Serial Programming Algorithm To program and verify the AT89S52 in the serial programming mode, the following sequence is recommended: 1. Power-up sequence: a. Apply power between VCC and GND pins. ...

Page 23

... X = don’t care. 1919D–MICRO–6/08 ALE/ EA/ PROG V P2.6 P2.7 PP (2) L 12V (3) L 12V H H (3) L 12V H H (3) L 12V (1) L 12V AT89S52 P2.4-0 P0.7-0 P3.3 P3.6 P3.7 Data A12 A12-8 OUT P0. P0.3, P0 1EH X 0000 52H X 0001 06H X 0010 P1.7-0 Address A7-0 ...

Page 24

... ADDR. P1.0-P1.7 0000H/1FFFH P2 A12 P2.6 P2.7 SEE FLASH P3.3 PROGRAMMING MODES TABLE P3.6 P3.7 XTAL2 3-33 MHz XTAL1 GND PSEN AT89S52 ADDR. P1.0-P1.7 0000H/1FFFH P2 A12 P2.6 P2.7 SEE FLASH P3.3 PROGRAMMING MODES TABLE P3.6 P3.7 XTAL 2 3-33 MHz XTAL1 ...

Page 25

... GHBL Min Max 11.5 12 CLCL 48 t CLCL 48 t CLCL 48 t CLCL 48 t CLCL CLCL 48 t CLCL CLCL 1.0 50 VERIFICATION ADDRESS t AVQV DATA OUT t GHAX t GHSL LOGIC 1 LOGIC EHQZ ELQV BUSY READY t WC AT89S52 Units MHz µs µs µs µs µs 25 ...

Page 26

... Figure 23-2. Flash Memory Serial Downloading 24. Flash Programming and Verification Waveforms – Serial Mode Figure 24-1. Serial Programming Waveforms AT89S52 26 AT89S52 INSTRUCTION P1.5/MOSI INPUT P1.6/MISO DATA OUTPUT P1.7/SCK CLOCK IN XTAL2 3-33 MHz XTAL1 GND RST 1919D–MICRO–6/08 ...

Page 27

... Byte 0 xxx Byte 0 } Each of the lock bit modes needs to be activated sequentially before Mode 4 can be executed. AT89S52 Byte 4 Operation xxxx xxxx 0110 1001 Enable Serial Programming (Output on while RST is high MISO) xxxx xxxx Chip Erase Flash memory ...

Page 28

... SCK Pulse Width Low SLSH t MOSI Setup to SCK High OVSH t MOSI Hold after SCK High SHOX t SCK Low to MISO Valid SLIV t Chip Erase Instruction Cycle Time ERASE t Serial Byte Write Cycle Time SWC AT89S52 OVSH SHOX SCK t SHSL = -40⋅ 85⋅ Min CLCL 8 t ...

Page 29

... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. = 4.0V to 5.5V, unless otherwise noted. CC Min -0.5 0.2 V -0.5 0.2 V 0 2 2 AT89S52 Max Units - 0. -50 µA -300 µA ± ...

Page 30

... Address Low AVWL t Data Valid to WR Transition QVWX t Data Valid to WR High QVWH t Data Hold After WR WHQX t RD Low to Address Float RLAZ High to ALE High WHLH AT89S52 30 12 MHz Oscillator Variable Oscillator Min Max Min 0 127 2t -40 CLCL 43 t -25 CLCL 48 t -25 ...

Page 31

... AVLL LLIV t LLPL t PLIV t PLAZ t LLAX INSTR IN t AVIV A8 - A15 t LHLL t LLDV t RLRH t LLWL t LLAX t RLDV t AVLL t RLAZ DATA IN t AVWL t AVDV P2 A15 FROM DPH t PLPH t PXAV t PXIZ PXIX A15 t WHLH t RHDZ t RHDX FROM PCL INSTR A15 FROM PCH AT89S52 31 ...

Page 32

... External Clock Drive Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL AT89S52 32 t LHLL t t LLWL WLWH t LLAX t t QVWX AVLL t QVWH DATA OUT t AVWL P2 A15 FROM DPH t ...

Page 33

... Timing Reference V LOAD Points V - 0.1V LOAD /V level occurs Variable Oscillator Max Min Max 12 t CLCL 10 t -133 CLCL 2 t -80 CLCL 0 700 10 t CLCL SET TI VALID VALID VALID VALID SET RI min. for a logic 1 and V max. for a logic 0. 0.1V OL AT89S52 Units μ -133 VALID 33 ...

Page 34

... Green Package Option (Pb/Halide-free) Speed Power (MHz) Supply Ordering Code AT89S52-24AU 24 4.0V to 5.5V AT89S52-24JU AT89S52-24PU AT89S52-33AU 33 4.5V to 5.5V AT89S52-33JU AT89S52-33PU 44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) ...

Page 35

... A1 0.05 – A2 0.95 1.00 D 11.75 12.00 D1 9.90 10.00 E 11.75 12.00 E1 9.90 10.00 B 0.30 – C 0.09 – L 0.45 – e 0.80 TYP DRAWING NO. AT89S52 MAX NOTE 1.20 0.15 1.05 12.25 10.10 Note 2 12.25 10.10 Note 2 0.45 0.20 0.75 10/5/2001 REV. 44A B 35 ...

Page 36

... Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT89S52 36 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER E1 E ...

Page 37

... A1 0.381 – D 52.070 – E 15.240 – E1 13.462 – B 0.356 – B1 1.041 – L 3.048 – C 0.203 – eB 15.494 – e 2.540 TYP DRAWING NO. AT89S52 MAX NOTE 4.826 – 52.578 Note 2 15.875 13.970 Note 2 0.559 1.651 3.556 0.381 17.526 09/28/01 REV. 40P6 B 37 ...

Page 38

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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