PIC24F04KA201-I/SS Microchip Technology, PIC24F04KA201-I/SS Datasheet

IC PIC MCU FLASH 512KX4 20-SSOP

PIC24F04KA201-I/SS

Manufacturer Part Number
PIC24F04KA201-I/SS
Description
IC PIC MCU FLASH 512KX4 20-SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr

Specifications of PIC24F04KA201-I/SS

Core Size
16-Bit
Program Memory Size
4KB (1.375K x 24)
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Number Of I /o
18
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Controller Family/series
PIC24
No. Of I/o's
18
Ram Memory Size
512Byte
Cpu Speed
32MHz
No. Of Timers
3
Processor Series
PIC24F
Core
PIC
Data Bus Width
16 bit
Data Ram Size
512 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
12
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 9 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
1.0
This document defines the programming specifications
for the PIC24FXXKA2XX family of 16-bit micro-
controller devices. This is required only for developing
programming support for the PIC24FXXKA2XX family.
Users of any one of these devices should use the
development tools that are already supporting the
device programming.
The programming specifications are specific to the
following devices:
• PIC24F04KA200
• PIC24F04KA201
TABLE 2-1:
 2010 Microchip Technology Inc.
MCLR/V
V
V
PGCx
PGDx
Legend: I = Input, O = Output, P = Power
DD
SS
Pin Name
PIC24FXXKA2XX Flash Programming Specifications
DEVICE OVERVIEW
PP
PIN DESCRIPTIONS (DURING PROGRAMMING)
MCLR/V
Pin Name
PGC
PGD
V
V
DD
SS
PP
Pin Type
I/O
P
P
P
I
PIC24FXXKA2XX
Programming Enable
Power Supply
Ground
Programming Pin Pair: Serial Clock
Programming Pin Pair: Serial Data
During Programming
2.0
PIC24FXXKA2XX family devices are programmed
exclusively using In-Circuit Serial Programming™
(ICSP™). This method provides native, low-level pro-
gramming capability to erase, program and verify the
device.
the ICSP method.
2.1
All devices in the PIC24FXXKA2XX family are
3.3V supply designs. The core, the peripherals and the
I/O pins operate at 3.3V. The device can operate from
1.8V to 3.6V.
Table 2-1
programming, which are indicated in
to the device data sheet for complete pin descriptions.
Note:
Section 3.0 “ICSP Programming”
PROGRAMMING OVERVIEW
OF THE PIC24FXXKA2XX
FAMILY
Power Requirements
provides the pins that are required for
Unlike
PIC24FXXKA2XX devices do not support
Enhanced ICSP programming. These
devices also do not support in-circuit
debugging over the ICSP interface.
Pin Description
other
PIC24F
Figure
DS39991A-page 1
2-1. Refer
devices,
describes

Related parts for PIC24F04KA201-I/SS

PIC24F04KA201-I/SS Summary of contents

Page 1

... Users of any one of these devices should use the development tools that are already supporting the device programming. The programming specifications are specific to the following devices: • PIC24F04KA200 • PIC24F04KA201 TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING) Pin Name Pin Name MCLR/V MCLR/V ...

Page 2

... PIC24FXXKA2XX PIC24FXXKA2XX FIGURE 2-1: 14-Pin SPDIP, SOIC 20-Pin SPDIP, SOIC 20-Pin QFN DS39991A-page 2 PIN DIAGRAMS MCLR PGC2 PGD2 PGD3 6 9 PGC3 MCLR PGC2 3 18 PGD2 PGD3 PGC3 PIC24F04KA201  2010 Microchip Technology Inc. ...

Page 3

... The Device ID registers read out normally even after code protection is applied. TABLE 2-2: PROGRAM MEMORY SIZES Program Memory Device Upper Address (Instruction Words) PIC24F04KA200 AFEh (1.375K) PIC24F04KA201 TABLE 2-3: CONFIGURATION REGISTER LOCATIONS Configuration Register Address FGS F80004 FOSCSEL F80006 FOSC ...

Page 4

... Exit ICSP Mode End TABLE 3-1: CPU CONTROL CODES IN ICSP™ MODE 4-Bit Mnemonic Description Control Code Shift in 24-bit instruction 0000 SIX and execute. Shift out the VISI 0001 REGOUT (0784h) register. N/A This is reserved. 0010-1111  2010 Microchip Technology Inc. ...

Page 5

... CPU forces a NOP while the new data is read. To account for this, while using ICSP, any indirect references to a recently modified register should be proceeded with a NOP.  2010 Microchip Technology Inc. PIC24FXXKA2XX For example, MOV [W0],W1 must have a NOP inserted in between. ...

Page 6

... P1A P1B LSB 24-Bit Instruction Fetch PGDx = Input ... LSb Shift Out VISI Register<15:0> PGDx = Output P4A MSB Execute 24-Bit Instruction, Fetch Next Control Code P4A 13 14 MSb Execution Takes Place, Fetch Next Control Code PGDx = Input  2010 Microchip Technology Inc. ...

Page 7

... Program/Verify Entry Code = 4D434851h PGDx 0 1 b31 b30 PGCx P18  2010 Microchip Technology Inc. PIC24FXXKA2XX interval of at least P19 and P7 must elapse before presenting data on PGDx. Signals appearing on PGCx before P7 has elapsed would not be interpreted as valid. 3.3.2 HIGH-VOLTAGE ICSP ENTRY Entering the ICSP Program/Verify mode, using the V pin is the same as entering the mode using MCLR ...

Page 8

... Erase four rows of code memory. Erase two rows of code memory. Erase a row of code memory. Erase all the Configuration registers (except the code-protect fuses). Erase Configuration registers except FBS and FGS. NVMCON VALUES FOR WRITE OPERATIONS Write Operation  2010 Microchip Technology Inc. ...

Page 9

... NOP Clock out the contents of the VISI register. 0001 <VISI> 0000 000000 NOP  2010 Microchip Technology Inc. PIC24FXXKA2XX FIGURE 3-6: Write 4064h to NVMCON SFR Set the WR bit to Initiate Erase Delay P11 + P10 Time Description 0x200 #0x4064, W10 W10, NVMCON #< ...

Page 10

... Finally, in Step 10, repeat Steps 3 through 9 until all of the code memory is programmed. FIGURE 3-7: PACKED INSTRUCTION WORDS IN W0: LSW0 W1 MSB1 W2 LSW1 W3 LSW2 W4 MSB3 W5 LSW3 Description 0x200 #0x4004, W10 W10, NVMCON #<DestinationAddress23:16>, W0 W0, TBLPAG #<DestinationAddress15:0>, W7  2010 Microchip Technology Inc MSB0 MSB2 ...

Page 11

... NOP Step 9: Reset device internal PC. 0000 040200 GOTO 0000 000000 NOP Step 10: Repeat Steps 3 through 9 until the entire code memory is programmed.  2010 Microchip Technology Inc. PIC24FXXKA2XX Description #<LSW0>, W0 #<MSB1:MSB0>, W1 #<LSW1>, W2 #<LSW2>, W3 #<MSB3:MSB2>, W4 #<LSW3> [W6++], [W7] [W6++], [W7++] [W6++], [++W7] ...

Page 12

... PROGRAM CODE MEMORY FLOW LoopCount = LoopCount + 1 DS39991A-page 12 Start LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at <Addr> All No bytes written? Yes Start Write Sequence and Poll for WR bit to be Cleared All No locations done? Yes End  2010 Microchip Technology Inc. ...

Page 13

... Reset vector is exited. In Step 2, the NVMCON register is initialized for programming code memory. In Step 3, the 24-bit starting destination address for programming is loaded into the TBLPAG register and W7 register. Note: The TBLPAG register must be loaded with F8h.  2010 Microchip Technology Inc. PIC24FXXKA2XX TABLE 3-6: Configuration Registers FGS FOSCSEL ...

Page 14

... Step 10: Repeat Steps 5 through 9 to write other fuses, Load W6 with their respective values and W7 with their respective addresses. DS39991A-page 14 Command (Binary) 0x200 #0x0000, W7 #0x4004, W10 W10, NVMCON #0xF8, W6 W0, TBLPAG #<FBS_VALUE>, W6 W6, [W7++] NVMCON, #WR 0x200 NVMCON, W2 W2, VISI 0x200  2010 Microchip Technology Inc. ...

Page 15

... FOSCSEL<2:0> Oscillator Selection bits Note 1: The MCLRE fuse can only be changed when using the V from accidentally locking out the device from low-voltage test entry.  2010 Microchip Technology Inc. PIC24FXXKA2XX Description Brown-out Reset Enable bits 11 = Brown-out Reset is enabled in hardware; SBOREN bit is disabled 10 = Brown-out Reset is enabled only while device is active and disabled in Sleep ...

Page 16

... Primary oscillator/external clock input frequency is less than 100 kHz 00 = Reserved; do not use Power-up Timer Enable bit 0 = PWRT is disabled 1 = PWRT is enabled Secondary Oscillator Select bit 1 = Secondary oscillator is configured for high-power operation 0 = Secondary oscillator is configured for low-power operation -Based Test mode entry. This prevents a user PP  2010 Microchip Technology Inc. ...

Page 17

... WDTPS<3:0> FWDT<3:0> WINDIS FWDT<6> Note 1: The MCLRE fuse can only be changed when using the V from accidentally locking out the device from low-voltage test entry.  2010 Microchip Technology Inc. PIC24FXXKA2XX Description Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 • ...

Page 18

... VISI register, using the REGOUT command. Step 4 is repeated until the required amount of code memory is read. Description 0x200 #<SourceAddress23:16>, W0 W0, TBLPAG #<SourceAddress15:0>, W6 #VISI, W7 [W6], [W7] [W6++], [W7] [++W6], [W7--] [W6++], [W7] 0x200 3-7). In Step 3, the Write  2010 Microchip Technology Inc. ...

Page 19

... Step 4: Repeat Step 3 to read other fuses. Load W6 with their respective address. Step 5: Reset device internal PC. 0000 040200 GOTO 0000 000000 NOP  2010 Microchip Technology Inc. PIC24FXXKA2XX Table 3-10 provides the ICSP programming details for reading all of the Configuration registers. Note: The TBLPAG ...

Page 20

... PGCx and PGDx before removing V FIGURE 3-10: Section 3.8 MCLR verified V DD PGDx PGCx Failure Report Error from IH Figure 3-10. The only . IH EXITING ICSP™ MODE P16 P17 IHH V IH PGD = Input  2010 Microchip Technology Inc. ...

Page 21

... Table 4-1 provides the Device ID for each device; Table 4-2 provides the Device ID registers; describes the bit field of each register. TABLE 4-1: DEVICE IDs Device ID DEVID PIC24F04KA200 0D02h PIC24F04KA201 0D00h TABLE 4-2: PIC24FXXKA2XX DEVICE ID REGISTERS Address Name 15 14 FF0000h DEVID FF0002h ...

Page 22

... Units Conditions V Normal programming A — mA — V — V — V — meet AC specifications ns — ns — ns — ns — ns — ns — ns — ns — ns — ms — ns — ms — ms — ms — s — ns — s — ns — ms — ms —  2010 Microchip Technology Inc. ...

Page 23

... APPENDIX A: REVISION HISTORY Rev A Document (9/2010) Original version of this document; takes all information specific to PIC24XXKA20X family devices, originally found in DS39919, and created a new specification. No technical information regarding the devices or their programming has changed.  2010 Microchip Technology Inc. PIC24FXXKA2XX DS39991A-page 23 ...

Page 24

... PIC24FXXKA2XX NOTES: DS39991A-page 24  2010 Microchip Technology Inc. ...

Page 25

... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 26

... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350  2010 Microchip Technology Inc. 08/04/10 ...

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