ATTINY85V-10PU Atmel, ATTINY85V-10PU Datasheet - Page 71
![IC AVR MCU 8K 10MHZ 8DIP](/photos/6/50/65033/313-8-dip_sml.jpg)
ATTINY85V-10PU
Manufacturer Part Number
ATTINY85V-10PU
Description
IC AVR MCU 8K 10MHZ 8DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY85V-10PU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
USI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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11.5
2586M–AVR–07/10
Output Compare Unit
Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
selected by the Clock Select bits (CS0[2:0]). When no clock source is selected (CS0[2:0] = 0)
the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of
whether clk
count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in
the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter
Control Register B (TCCR0B). There are close connections between how the counter behaves
(counts) and how waveforms are generated on the Output Compare output OC0A. For more
details about advanced counting sequences and waveform generation, see
tion” on page
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by
the WGM0[1:0] bits. TOV0 can be used for generating a CPU interrupt.
The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers
(OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a
match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock
cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output
Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe-
cuted. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit
location. The Waveform Generator uses the match signal to generate an output according to
operating mode set by the WGM0[2:0] bits and Compare Output mode (COM0x[1:0]) bits. The
max and bottom signals are used by the Waveform Generator for handling the special cases of
the extreme values in some modes of operation
Figure 11-5
Figure 11-5. Output Compare Unit, Block Diagram
T0
shows a block diagram of the Output Compare unit.
bottom
FOCn
74.
is present or not. A CPU write overrides (has priority over) all counter clear or
top
OCRnx
T0
). clk
T0
can be generated from an external or internal clock source,
Waveform Generator
WGMn[1:0]
=
(8-bit Comparator )
DATA BUS
(See “Modes of Operation” on page
COMnX[1:0]
TCNTn
OCFnx (Int.Req.)
OCnx
“Modes of Opera-
74.).
71
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