PIC16LF726-I/SP Microchip Technology, PIC16LF726-I/SP Datasheet - Page 171
![IC PIC MCU FLASH 8K 1.8V 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC16LF726-I/SP
Manufacturer Part Number
PIC16LF726-I/SP
Description
IC PIC MCU FLASH 8K 1.8V 28-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Specifications of PIC16LF726-I/SP
Core Size
8-Bit
Program Memory Size
14KB (8K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
25
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC16LF
No. Of I/o's
25
Ram Memory Size
368Byte
Cpu Speed
20MHz
No. Of Timers
3
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
25
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF726-I/SP
Manufacturer:
Microchip Technology
Quantity:
135
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17.1.2
For any SPI device acting as a slave, the data is
transmitted and received as external clock pulses
appear on SCK pin. This external clock must meet the
minimum high and low times as specified in the
electrical specifications.
17.1.2.1
The SSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready.
The slave has no control as to when data will be
clocked in or out of the device. All data that is to be
transmitted, to a master or another slave, must be
loaded into the SSPBUF register before the first clock
pulse is received.
Once eight bits of data have been received:
• Received byte is moved to the SSPBUF register
• BF bit of the SSPSTAT register is set
• SSPIF bit of the PIR1 register is set
Any
transmission/reception of data will be ignored and the
Write Collision Detect bit, WCOL of the SSPCON
register, will be set. User software must clear the
WCOL bit so that it can be determined if the following
write(s)
successfully.
The user’s firmware must read SSPBUF, clearing the
BF flag, or the SSPOV bit of the SSPCON register will
be set with the reception of the next byte and
communication will be disabled.
A SPI module transmits and receives at the same time,
occasionally
transmitted/received. It is up to the user to determine
which data is to be used and what can be discarded.
© 2009 Microchip Technology Inc.
write
to
SLAVE MODE
Slave Mode Operation
to
the
causing
the
SSPBUF
SSPBUF
dummy
register
register
data
completed
to
during
be
PIC16F72X/PIC16LF72X
17.1.2.2
To enable the serial port, the SSPEN bit of the
SSPCON register must be set. If a Slave mode of
operation is selected in the SSPM bits of the SSPCON
register, the SDI, SDO, SCK pins will be assigned as
serial port pins.
For these pins to function as serial port pins, they must
have their corresponding data direction bits set or
cleared in the associated TRIS register as follows:
• SDI configured as input
• SDO configured as output
• SCK configured as input
Optionally, a fourth pin, Slave Select (SS) may be used
in Slave mode. Slave Select may be configured to
operate on one of the following pins via the SSSEL bit in
the APFCON register.
• RA5/AN4/SS
• RA0/AN0/SS
Upon selection of a Slave Select pin, the appropriate
bits must be set in the ANSELA and TRISA registers.
Slave Select must be set as an input by setting the
corresponding bit in TRISA, and digital I/O must be
enabled on the SS pin by clearing the corresponding bit
of the ANSELA register.
17.1.2.3
When initializing the SSP module to SPI Slave mode,
compatibility must be ensured with the master device.
This is done by programming the appropriate control
bits of the SSPCON and SSPSTAT registers. These
control bits allow the following to be specified:
• SCK as clock input
• Idle state of SCK (CKP bit)
• Data input sample phase (SMP bit)
• Output data on rising/falling edge of SCK (CKE bit)
Figure 17-4 and Figure 17-5 show example waveforms
of Slave mode operation.
Enabling Slave I/O
Slave Mode Setup
DS41341E-page 171
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