PIC18F13K22-I/SO Microchip Technology, PIC18F13K22-I/SO Datasheet - Page 67
![IC MCU 8BIT 8KB FLASH 20SOIC](/photos/6/64/66480/150-20-soic_sml.jpg)
PIC18F13K22-I/SO
Manufacturer Part Number
PIC18F13K22-I/SO
Description
IC MCU 8BIT 8KB FLASH 20SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF13K22-ISS.pdf
(388 pages)
2.PIC18LF13K22-ISS.pdf
(12 pages)
3.PIC18F13K22-ISS.pdf
(382 pages)
Specifications of PIC18F13K22-I/SO
Program Memory Type
FLASH
Program Memory Size
8KB (4K x 16)
Package / Case
20-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, MSSP, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Package
20SOIC W
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
A/d Bit Size
10 bit
A/d Channels Available
12
Height
2.05 mm
Length
12.8 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V, 2.7 V
Width
7.5 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F13K22-I/SO
Manufacturer:
Microchip Technology
Quantity:
1 865
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7.4
The INTCON registers are readable and writable
registers, which contain various enable, priority and
flag bits.
REGISTER 7-1:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
GIE/GIEH
R/W-0
2:
INTCON Registers
A mismatch condition will continue to set the RABIF bit. Reading PORTA and PORTB will end the
mismatch condition and allow the bit to be cleared.
RA and RB port change interrupts also require the individual pin IOCA and IOCB enable.
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts including peripherals
When IPEN = 1:
1 = Enables all high priority interrupts
0 = Disables all interrupts including low priority
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low priority interrupts
0 = Disables all low priority interrupts
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
RABIE: RA and RB Port Change Interrupt Enable bit
1 = Enables the RA and RB port change interrupt
0 = Disables the RA and RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared by software)
0 = TMR0 register did not overflow
INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared by software)
0 = The INT0 external interrupt did not occur
RABIF: RA and RB Port Change Interrupt Flag bit
1 = At least one of the RA <5:0> or RB<7:4> pins changed state (must be cleared by software)
0 = None of the RA<5:0> or RB<7:4> pins have changed state
PEIE/GIEL
R/W-0
INTCON: INTERRUPT CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
TMR0IE
R/W-0
INT0IE
R/W-0
Preliminary
PIC18F1XK22/LF1XK22
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(1)
RABIE
R/W-0
(2)
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
TMR0IF
R/W-0
x = Bit is unknown
INT0IF
R/W-0
DS41365B-page 65
RABIF
R/W-x
bit 0
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