PIC16LF1938-I/ML Microchip Technology, PIC16LF1938-I/ML Datasheet - Page 283

• Manufacturer Part Number: PIC16LF1938-I/ML
• Description: IC MCU 8BIT FLASH 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1938-I/ML

• Core Size: 8-Bit
• Program Memory Size: 28KB (16K x 14)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16LF
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 1024Byte
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.7
The MSSP module has a Baud Rate Generator avail-
able for clock generation in both I
modes. The Baud Rate Generator (BRG) reload value
is placed in the SSPADD register (Register 23-6).
When a write occurs to SSPBUF, the Baud Rate Gen-
erator will automatically begin counting down.
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
An internal signal “Reload” in Figure 23-39 triggers the
value from SSPADD to be loaded into the BRG counter.
This occurs twice for each oscillation of the module
FIGURE 23-40:
TABLE 23-4:
 2009 Microchip Technology Inc.
Note 1:
Note: Values of 0x00, 0x01 and 0x02 are not valid
Baud Rate Generator
for SSPADD when used as a Baud Rate
Generator for I
limitation.
32 MHz
32 MHz
32 MHz
16 MHz
16 MHz
16 MHz
4 MHz
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
F
OSC
2
C interface does not conform to the 400 kHz I
MSSP CLOCK RATE W/BRG
BAUD RATE GENERATOR BLOCK DIAGRAM
2
C. This is an implementation
SSPM<3:0>
SCL
2
C and SPI Master
8 MHz
8 MHz
8 MHz
4 MHz
4 MHz
4 MHz
1 MHz
SSPM<3:0>
F
CY
Control
Reload
SSPCLK
Preliminary
Reload
clock line. The logic dictating when the reload signal is
asserted depends on the mode the MSSP is being
operated in.
Table 23-4 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
EQUATION 23-1:
2
C specification (which applies to rates greater than
BRG Down Counter
PIC16F193X/LF193X
SSPADD<7:0>
BRG Value
0Ch
4Fh
13h
19h
09h
27h
09h
F
CLOCK
=
-------------------------------------------------

SSPxADD
F
OSC
(2 Rollovers of BRG)
/2
F
OSC
400 kHz
400 kHz
DS41364D-page 283
308 kHz
100 kHz
308 kHz
100 kHz
100 kHz
F
+
CLOCK
1
 4  
(1)
(1)