PIC16F628A-I/P Microchip Technology, PIC16F628A-I/P Datasheet - Page 93
![IC MCU FLASH 2KX14 EEPROM 18DIP](/photos/6/76/67657/18-dip_300mil__sml.jpg)
PIC16F628A-I/P
Manufacturer Part Number
PIC16F628A-I/P
Description
IC MCU FLASH 2KX14 EEPROM 18DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F627A-IP.pdf
(180 pages)
2.PIC16F627A-IP.pdf
(22 pages)
3.PIC16F627A-ISO.pdf
(168 pages)
4.PIC16F648A-ISS.pdf
(178 pages)
Specifications of PIC16F628A-I/P
Program Memory Type
FLASH
Program Memory Size
3.5KB (2K x 14)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
128 x 8
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
224 B
Interface Type
SCI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
Package
18PDIP
Device Core
PIC
Family Name
PIC16
Maximum Speed
20 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3DBF648 - BOARD DAUGHTER ICEPIC3AC162053 - HEADER INTERFACE ICD,ICD2 18DIPACICE0202 - ADAPTER MPLABICE 18P 300 MILAC164010 - MODULE SKT PROMATEII DIP/SOIC
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F628A-I/P
Manufacturer:
BT
Quantity:
562
Company:
Part Number:
PIC16F628A-I/P
Manufacturer:
MICROCHI
Quantity:
850
Part Number:
PIC16F628A-I/P
Manufacturer:
MICROCHIP
Quantity:
20 000
13.3
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON1<0>). The data is available, in the very
next cycle, in the EEDATA register; therefore it can be
read in the next instruction. EEDATA will hold this value
until another read or until it is written to by the user
(during a write operation).
EXAMPLE 13-1:
13.4
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte.
EXAMPLE 13-2:
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number what is not equal to
the required cycles to execute the required sequence
will cause the data not to be written into the EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
2004 Microchip Technology Inc.
BSF
MOVLW
MOVWF
BSF
MOVF
BCF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF INTCON, GIE
READING THE EEPROM DATA
MEMORY
WRITING TO THE EEPROM DATA
MEMORY
STATUS, RP0
CONFIG_ADDR
EEADR
EECON1, RD
EEDATA, W
STATUS, RP0
STATUS, RP0
EECON1, WREN
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1,WR
DATA EEPROM READ
DATA EEPROM WRITE
;Bank 1
;
;Address to read
;EE Read
;W = EEDATA
;Bank 0
;Bank 1
;Enable write
;Disable INTs.
;
;Write 55h
;
;Write AAh
;Set WR bit
;begin write
;Enable INTs.
Preliminary
PIC16F627A/628A/648A
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit in the
PIR1 registers must be cleared by software.
13.5
Depending on the application, good programming
practice may dictate that the value written to the Data
EEPROM should be verified (Example 13-3) to the
desired value to be written. This should be used in
applications where an EEPROM bit will be stressed
near the specification limit.
EXAMPLE 13-3:
13.6
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also
when enabled, the Power-up Timer (72 ms duration)
prevents EEPROM write.
The write initiate sequence, and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
;
;Is the value written (in W reg) and
;read (in EEDATA) the same?
;
BSF
MOVF
BSF
SUBWF EEDATA, W
BTFSS STATUS, Z
GOTO
:
:
WRITE VERIFY
PROTECTION AGAINST
SPURIOUS WRITE
STATUS, RP0 ;Bank 1
EEDATA, W
EECON1, RD ;Read the
WRITE_ERR
WRITE VERIFY
;value written
;
;Is difference 0?
;NO, Write error
;YES, Good write
;Continue program
DS40044B-page 91