ATMEGA48V-10MU Atmel, ATMEGA48V-10MU Datasheet - Page 33

• Manufacturer Part Number: ATMEGA48V-10MU
• Description: IC AVR MCU 4K 10MHZ 1.8V 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA48V-10MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Package: 32MLF EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 10 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 23
• Interface Type: SPI/TWI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Processor Series: ATMEGA48x
• Core: AVR8
• Data Ram Size: 512 B
• Maximum Clock Frequency: 10 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 10MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.18
2545SS–AVR–07/10
Rev. 2545B-01/04
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Added section
Added item 2 to 5 in
Updated C code examples containing old IAR syntax.
Added PDIP to “I/O and Packages”, updated “Speed Grade” and Power Consumption
Estimates in
Updated
value.
of the PRR bits to 2-wire, Timer/Counters, USART, Analog Comparator and ADC
sections.
Updated
Updated
Extra Compare Match Interrupt OCF2B added to features in section
Timer/Counter2 with PWM and Asynchronous Operation” on page 139
Updated
page 285 to 287 and
284. Fixed typo in
Updated whole
Renamed the following bits:
- SPMEN to SELFPRGEN
- PSR2 to PSRASY
- PSR10 to PSRSYNC
- Watchdog Reset to Watchdog System Reset
Updated BLBSET description in
Status Register” on page
“Watchdog Timer” on page
Figure 15-2 on page 129
Table 9-1 on page
“Stack Pointer” on page 12
35.“Features” on page
“Power Reduction Register” on page 40
“Typical Characteristics” on page
Table 12-1 on page
“Errata ATmega48” on page
Table 23-1 on page
282.
38,
Table 23-5 on page
“SPMCSR – Store Program Memory Control and
and
1.
48.
with RAMEND as recommended Stack Pointer
66.
Table 15-3 on page
248. Added note 2 to
314.
357.
258,
ATmega48/88/168
and a note regarding the use
Table 27-4
130.
Table 27-1 on page
to
Table 27-7
“8-bit
on
33