PIC24F08KA101-I/MQ Microchip Technology, PIC24F08KA101-I/MQ Datasheet - Page 34
![IC PIC MCU FLASH 1KX8 20-QFN](/photos/6/98/69844/c04-139_mq_sml.jpg)
PIC24F08KA101-I/MQ
Manufacturer Part Number
PIC24F08KA101-I/MQ
Description
IC PIC MCU FLASH 1KX8 20-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.MA240017.pdf
(254 pages)
2.PIC24F04KA201-ISS.pdf
(48 pages)
3.PIC24F16KA101-ISS.pdf
(18 pages)
Specifications of PIC24F08KA101-I/MQ
Program Memory Type
FLASH
Program Memory Size
8KB (2.75K x 24)
Package / Case
20-VQFN
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Eeprom Size
512 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24F
Core
PIC
Data Bus Width
16 bit
Data Ram Size
1.5 KB
Interface Type
I2C/IrDA/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
PIC24FXXKAXXX
5.2.2
When 24-bit instruction words are transferred across
the 16-bit SPI interface, they are packed to conserve
space using the format illustrated in Figure 5-5. This
format minimizes the traffic over the SPI and provides
the programming executive the data that is properly
aligned for performing table write operations.
FIGURE 5-5:
TABLE 5-1:
DS39919A-page 34
Legend: TBD = To Be Determined
Note 1:
Opcode Mnemonic
LSWx: Least Significant 16 bits of instruction word
MSbx: Most Significant bits of instruction word
Note:
15
Ch
Dh
Ah
Bh
Eh
Fh
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
SCHECK
READC
READP
RESERVED
PROGC
PROGP
RESERVED
RESERVED
RESERVED
RESERVED
QBLANK
QVER
READD
PROGD
RESERVED
RESERVED
MSb2
One row of code memory consists of (32) 24-bit words. Refer to Table 2-3 for device-specific information.
PACKED DATA FORMAT
When the number of instruction words
transferred is odd, MSb2 is zero and
LSW2 cannot be transmitted.
PROGRAMMING EXECUTIVE COMMAND SET
PACKED INSTRUCTION
WORD FORMAT
LSW1
LSW2
8 7
(16-bit words)
Length
N/A
N/A
N/A
N/A
N/A
N/A
N/A
99
19
1
3
4
4
3
1
4
MSb1
1 msec/word Read up to (256) 16-bit words starting from the specified
1 msec/row Read up to 32K instruction words of code memory starting
Time-out
1 msec
1 msec
5 msec
5 msec
1 msec
5 msec
Advance Information
TBD
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
Sanity check.
Read up to (256) 8-bit words starting from the specified Device
ID register.
from the specified address.
This command is reserved; it returns a NACK.
Write an 8-bit word to the specified Device ID registers.
Program up to 32 instructions (one row) of code memory at the
specified address and then verify.
This command is reserved; it returns a NACK.
This command is reserved; it returns a NACK.
This command is reserved; it returns a NACK.
This command is reserved; it returns a NACK.
Query if the code memory is blank.
Query the programming executive software version.
This command is reserved; it returns a NACK.
This command is reserved. it returns a NACK.
address.
Program one word of data EEPROM memory at the specified
address and then verify.
5.2.3
The
unsupported commands. Additionally, due to the
memory constraints of the programming executive, no
checking is performed on the data contained in the
programmer command. It is the responsibility of the
programmer to command the programming executive
with valid command arguments; otherwise, the
programming operation might fail. Section 5.3.1.3
“QE_Code Field” provides additional information on
error handling.
programming
PROGRAMMING EXECUTIVE
ERROR HANDLING
Description
(1)
executive
© 2008 Microchip Technology Inc.
(1)
(1)
will
“NACK”
all