PIC16F724-I/ML Microchip Technology, PIC16F724-I/ML Datasheet - Page 164
![IC PIC MCU FLASH 4KX14 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC16F724-I/ML
Manufacturer Part Number
PIC16F724-I/ML
Description
IC PIC MCU FLASH 4KX14 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.AC164112.pdf
(302 pages)
2.PIC16F722-ISS.pdf
(8 pages)
3.PIC16F722-ISS.pdf
(10 pages)
4.PIC16F722-ISS.pdf
(32 pages)
5.PIC16F722-ISS.pdf
(2 pages)
6.PIC16F722-ISS.pdf
(8 pages)
7.PIC16LF724-IPT.pdf
(266 pages)
Specifications of PIC16F724-I/ML
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Oscillator Type
Internal
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 14x8b
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Controller Family/series
PIC16F
No. Of I/o's
36
Ram Memory Size
192Byte
Cpu Speed
20MHz
No. Of Timers
3
No. Of Pwm
RoHS Compliant
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
192 B
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
36
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 14 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN444-1001 - DEMO BOARD FOR PICMICRO MCU
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- AC164112 PDF datasheet
- PIC16F722-ISS PDF datasheet #2
- PIC16F722-ISS PDF datasheet #3
- PIC16F722-ISS PDF datasheet #4
- PIC16F722-ISS PDF datasheet #5
- PIC16F722-ISS PDF datasheet #6
- PIC16LF724-IPT PDF datasheet #7
- Current page: 164 of 266
- Download datasheet (5Mb)
PIC16F72X/PIC16LF72X
FIGURE 16-8:
TABLE 16-7:
DS41341A-page 162
INTCON
PIE1
PIR1
RCREG
RCSTA
TRISC
TXSTA
Legend:
(SCKP = 0)
(SCKP = 1)
(Interrupt)
Note:
Name
TX/CK pin
TX/CK pin
SREN bit
CREN bit
bit SREN
RCIF bit
RXREG
RX/DT
Write to
Read
pin
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception.
AUSART Receive Data Register
Timing diagram demonstrates Synchronous Master mode with bit SREN = 1 and bit BRGH = 0.
TMR1GIE
‘0’
TMR1GIF
TRISC7
SPEN
CSRC
Bit 7
GIE
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TRISC6
ADIE
Bit 6
PEIE
ADIF
RX9
TX9
bit 0
TRISC5
SREN
TXEN
RCIE
RCIF
Bit 5
T0IE
bit 1
TRISC4
CREN
SYNC
Bit 4
INTE
TXIE
TXIF
bit 2
Preliminary
TRISC3
ADDEN
SSPIE
SSPIF
RBIE
Bit 3
—
bit 3
CCP1IE
CCP1IF
TRISC2
BRGH
FERR
Bit 2
T0IF
bit 4
TMR2IE
TMR2IF
TRISC1
OERR
TRMT
INTF
Bit 1
bit 5
TMR1IE
TMR1IF
TRISC0
RX9D
TX9D
RBIF
Bit 0
© 2007 Microchip Technology Inc.
bit 6
0000 000x
0000 0000
0000 0000
0000 0000
0000 000X
1111 1111
0000 -010
POR, BOR
Value on
bit 7
0000 000x
0000 0000
0000 0000
0000 0000
0000 000X
1111 1111
0000 -010
Value on
all other
Resets
‘0’
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