PIC18LF14K50-I/MQ Microchip Technology, PIC18LF14K50-I/MQ Datasheet - Page 73
![IC PIC MCU FLASH 768KX16 20-QFN](/photos/6/98/69844/c04-139_mq_sml.jpg)
PIC18LF14K50-I/MQ
Manufacturer Part Number
PIC18LF14K50-I/MQ
Description
IC PIC MCU FLASH 768KX16 20-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F13K50-ISS.pdf
(420 pages)
2.PIC18F13K50-ISS.pdf
(40 pages)
3.PIC18F13K50-ISS.pdf
(10 pages)
4.PIC18F13K50-ISS.pdf
(2 pages)
5.PIC18F14K50-IP.pdf
(422 pages)
Specifications of PIC18LF14K50-I/MQ
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
20-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART/I2C/MSSP/SPI/USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
15
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Controller Family/series
PIC18
No. Of I/o's
15
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
48MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF14K50-I/MQ
Manufacturer:
Microchip
Quantity:
270
- PIC18F13K50-ISS PDF datasheet
- PIC18F13K50-ISS PDF datasheet #2
- PIC18F13K50-ISS PDF datasheet #3
- PIC18F13K50-ISS PDF datasheet #4
- PIC18F14K50-IP PDF datasheet #5
- Current page: 73 of 420
- Download datasheet (4Mb)
7.5
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Request Flag registers (PIR1 and PIR2).
REGISTER 7-4:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
U-0
—
PIR Registers
Unimplemented: Read as ‘0’
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared by software)
0 = The A/D conversion is not complete or has not been started
RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The EUSART receive buffer is empty
TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The EUSART transmit buffer is full
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared by software)
0 = Waiting to transmit/receive
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared by software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared by software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared by software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared by software)
0 = TMR1 register did not overflow
R/W-0
ADIF
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
W = Writable bit
‘1’ = Bit is set
RCIF
R-0
TXIF
R-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPIF
R/W-0
Note 1: Interrupt flag bits are set when an inter-
2: User software should ensure the appro-
PIC18F/LF1XK50
rupt condition occurs, regardless of the
state of its corresponding enable bit or the
Global Interrupt Enable bit, GIE of the
INTCON register.
priate interrupt flag bits are cleared prior
to enabling an interrupt and after servicing
that interrupt.
CCP1IF
R/W-0
x = Bit is unknown
TMR2IF
R/W-0
DS41350E-page 73
TMR1IF
R/W-0
bit 0
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