PIC16LF628A-I/SO Microchip Technology, PIC16LF628A-I/SO Datasheet - Page 51
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PIC16LF628A-I/SO
Manufacturer Part Number
PIC16LF628A-I/SO
Description
IC MCU FLASH 2KX14 EEPROM 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F627A-IP.pdf
(180 pages)
2.PIC16LF627A-IP.pdf
(8 pages)
3.PIC16F648A-ISS.pdf
(178 pages)
4.PIC16LF627A-ISO.pdf
(180 pages)
Specifications of PIC16LF628A-I/SO
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Controller Family/series
PIC16LF
No. Of I/o's
16
Eeprom Memory Size
128Byte
Ram Memory Size
224Byte
Cpu Speed
20MHz
No. Of Timers
3
Package
18SOIC W
Device Core
PIC
Family Name
PIC16
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
16
Interface Type
USART
Number Of Timers
3
Processor Series
PIC16LF
Core
PIC
Data Ram Size
224 B
Maximum Clock Frequency
20 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF628A-I/SO
Manufacturer:
MICROCHIP
Quantity:
1 042
Part Number:
PIC16LF628A-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
7.1
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is F
(T1CON<2>) has no effect since the internal clock is
always in sync.
7.2
Counter mode is selected by setting bit TMR1CS. In
this mode, the TMR1 register pair value increments on
every rising edge of clock input on pin RB7/T1OSI/PGD
when bit T1OSCEN is set or pin RB6/T1OSO/T1CKI/
PGC when bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple-counter.
In this configuration, during Sleep mode, the TMR1
register pair value will not increment even if the
external clock is present, since the synchronization
circuit is shut off. The prescaler however will continue
to increment.
FIGURE 7-1:
© 2009 Microchip Technology Inc.
RB6/T1OSO/T1CKI/PGC
RB7/T1OSI/PGD
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
Timer1 Operation in Timer Mode
Timer1 Operation in Synchronized
Counter Mode
OSC
Set flag bit
TMR1IF on
Overflow
/4. The synchronize control bit T1SYNC
TIMER1 BLOCK DIAGRAM
TMR1H
T1OSC
TMR1
TMR1L
Oscillator
Enable
T1OSCEN
(1)
Clock
F
Internal
OSC
/4
PIC16F627A/628A/648A
TMR1ON
TMR1CS
1
0
7.2.1
When an external clock input is used for Timer1 in
Synchronized Counter mode, it must meet certain
requirements. The external clock requirement is due to
internal phase clock (T
there is a delay in the actual incrementing of the TMR1
register pair value after synchronization.
When the prescaler is 1:1, the external clock input is
the same as the prescaler output. The synchronization
of T1CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T1CKI to be high for at least 2 T
a small RC delay of 20 ns) and low for at least 2 T
(and a small RC delay of 20 ns). Refer to Table 17-8 in
the Electrical Specifications Section, timing parameters
45, 46 and 47.
When a prescaler other than 1:1 is used, the external
clock input is divided by the asynchronous ripple-counter
type prescaler so that the prescaler output is symmetri-
cal. In order for the external clock to meet the sampling
requirement, the ripple-counter must be taken into
account. Therefore, it is necessary for T1CKI to have a
period of at least 4 T
divided by the prescaler value. The only requirement on
T1CKI high and low time is that they do not violate the
minimum pulse width requirements of 10 ns). Refer to
the appropriate electrical specifications in Table 17-8,
parameters 45, 46 and 47.
T1SYNC
T1CKPS<1:0>
Prescaler
1, 2, 4, 8
EXTERNAL CLOCK INPUT TIMING
FOR SYNCHRONIZED COUNTER
MODE
0
1
2
OSC
(and a small RC delay of 40 ns)
Synchronized
OSC
Clock Input
Synchronize
Sleep Input
) synchronization. Also,
det
DS40044G-page 51
OSC
(and
OSC