PIC18F24J11-I/SO Microchip Technology, PIC18F24J11-I/SO Datasheet - Page 439

• Manufacturer Part Number: PIC18F24J11-I/SO
• Description: IC PIC MCU FLASH 16K 2V 28-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F24J11-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILAC164332 - MODULE SKT FOR 28SOIC 18F45J10
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

RETURN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2009 Microchip Technology Inc.
Q Cycle Activity:
After Instruction:
operation
Decode
No
PC = TOS
Q1
operation
operation
Return from Subroutine
RETURN {s}
s ∈ [0,1]
(TOS) → PC;
if s = 1,
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
None
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
‘s’= 1, the contents of the shadow
registers WS, STATUSS and BSRS are
loaded into their corresponding
registers W, STATUS and BSR. If
‘s’ = 0, no update of these registers
occurs (default).
1
2
RETURN
0000
No
No
Q2
0000
operation
Process
Data
No
Q3
0001
from stack
operation
POP PC
No
Q4
001s
PIC18F46J11 FAMILY
RLCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
C
REG
W
C
Q1
Rotate Left f through Carry
The contents of register ‘f’ are rotated
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f<n>) → dest<n + 1>,
(f<7>) → C,
(C) → dest<0>
C, N, Z
one bit to the left through the Carry flag.
If ‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in register
‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
register ‘f’
=
=
=
=
=
RLCF
Read
0011
RLCF
Q2
1110 0110
0
1110 0110
1100 1100
1
C
f {,d {,a}}
01da
Process
REG, 0, 0
Data
Q3
register f
DS39932C-page 439
ffff
destination
Write to
Q4
ffff