PIC24F08KA102-I/SP Microchip Technology, PIC24F08KA102-I/SP Datasheet - Page 2

• Manufacturer Part Number: PIC24F08KA102-I/SP
• Description: IC PIC MCU FLASH 8K 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F08KA102-I/SP

• Core Size: 16-Bit
• Program Memory Size: 8KB (2.75K x 24)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC24
• No. Of I/o's: 24
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1.5KB
• Cpu Speed: 32MHz
• No. Of Timers: 3
• Processor Series: PIC24F
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 1.5 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 32 KHz
• Number Of Programmable I/os: 24
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
• Lead Free Status / Rohs Status: Details

PIC24F16KA102 FAMILY
TABLE 2:
DS80473F-page 2
CTMU
Resets
Core
Core
Memory
Comparator
SPI
I/O Ports
I/O Ports
Core
Comparator
Comparator
Core
Note 1:
Module
Only those issues indicated in the last column apply to the current silicon revision.
BOR
ICSP™
Deep Sleep
Code
Protection
Enhanced
Buffer mode
PORTA and
PORTB
PORTA and
PORTB
Low-Voltage
BOR
I/O Pins
Doze mode
SILICON ISSUE SUMMARY
Feature
—
—
—
Number
Item
10.
12.
13.
11.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Module operates in Sleep mode.
Inadvertent Reset when disabling/enabling
BOR.
conditions.
Failure to avoid Deep Sleep entry.
No direct jump to Boot Sector from
Reset Vector.
Errors when polling SPITBF flag.
Under certain conditions, functionality for
RB0 and RA0 pins do not work correctly.
Under certain conditions, functionality for
RB2 does not work correctly.
LPBOR configuration results in ambiguous
Resets.
some digital I/O ports.
Output polarity inversion also inverts
edge-detect sensing.
Instruction execution glitches following
DOZE bit changes.
Unable to use PGC/PGD pair under certain
Change in maximum V
Enabling comparator outputs disables
Issue Summary
IOFF
.
 2010 Microchip Technology Inc.
A5
X
X
X
X
X
X
X
X
X
X
X
X
X
Affected Revisions
A6
X
X
X
X
X
X
X
X
X
X
X
A7
X
X
X
X
X
X
X
X
X
X
X
(1)
B0
X
X
X
X