PIC16F628A-I/SS Microchip Technology, PIC16F628A-I/SS Datasheet - Page 39

• Manufacturer Part Number: PIC16F628A-I/SS
• Description: IC MCU FLASH 2KX14 EEPROM 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F628A-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SCI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 20 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPI3DBF648 - BOARD DAUGHTER ICEPIC3AC164307 - MODULE SKT FOR PM3 28SSOPAC162053 - HEADER INTERFACE ICD,ICD2 18DIPAC164018 - MODULE SKT PROMATEII 20SSOP
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 5-9:
© 2009 Microchip Technology Inc.
WR TRISB
RD TRISB
RBPU
WR PORTB
Peripheral OE
RD PORTB
SPEN
USART Data Output
Data Bus
Note
USART Receive Input
1:
Peripheral OE (output enable) is only active if
peripheral select is active.
(1)
TRIS Latch
Data Latch
D
D
CK
CK
BLOCK DIAGRAM OF
RB1/RX/DT PIN
Q
Q
Schmitt
Q
Trigger
Q
Q
EN
1
0
D
TTL
Input
Buffer
V
P
DD
V
V
Weak
Pull-up
DD
SS
RX/DT
RB1/
PIC16F627A/628A/648A
FIGURE 5-10:
WR PORTB
WR TRISB
Peripheral OE
RD TRISB
RD PORTB
RBPU
SPEN
USART TX/CK Output
Data Bus
Note
USART Slave Clock In
1:
Peripheral OE (output enable) is only active if
peripheral select is active.
(1)
TRIS Latch
Data Latch
D
D
CK
CK
BLOCK DIAGRAM OF
RB2/TX/CK PIN
Q
Q
Schmitt
Q
Q
Trigger
Q
EN
1
0
D
DS40044G-page 39
TTL
Input
Buffer
V
P
DD
Weak
Pull-up
V
V
DD
SS
TX/CK
RB2/