PIC18LF14K22-I/P Microchip Technology, PIC18LF14K22-I/P Datasheet - Page 219
![IC PIC MCU FLASH 512KX16 20-PDIP](/photos/12/13/121303/150-20-dip_sml.jpg)
PIC18LF14K22-I/P
Manufacturer Part Number
PIC18LF14K22-I/P
Description
IC PIC MCU FLASH 512KX16 20-PDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF13K22-ISS.pdf
(388 pages)
2.PIC18LF13K22-ISS.pdf
(12 pages)
3.PIC18LF13K22-ISS.pdf
(36 pages)
4.PIC18LF14K22-IP.pdf
(382 pages)
Specifications of PIC18LF14K22-I/P
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
20-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, MSSP, SPI, USART
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC18LF13K22-ISS PDF datasheet
- PIC18LF13K22-ISS PDF datasheet #2
- PIC18LF13K22-ISS PDF datasheet #3
- PIC18LF14K22-IP PDF datasheet #4
- Current page: 219 of 382
- Download datasheet (6Mb)
FIGURE 17-3:
© 2009 Microchip Technology Inc.
V
FVR
C2RSEL
REF
C12IN0-
C12IN1-
C12IN2-
C12IN3-
C2IN+
C2CH<1:0>
0
1
MUX
C2V
COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM
C2R
REF
Note 1:
0
1
0
1
2
3
MUX
2
MUX
2:
3:
4:
C2V
C2V
When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.
Q1 and Q3 are phases of the four-phase system clock (F
Q1 is held high during Sleep mode.
Positive going pulse generated on both falling and rising edges of the bit.
C2SP
IN
IN
-
+
C2
From TMR1L[0]
C2ON
C2POL
Preliminary
(1)
Q3*RD_CM2CON0
PIC18F1XK22/LF1XK22
(4)
Q1
D
NRESET
Q
C2OUT
D
EN
C2SYNC
Q
D
EN
0
1
CL
Q
OSC
C20E
RD_CM2CON0
SYNCC2OUT
To PWM Logic
).
Data Bus
Set C2IF
C2OUT pin
DS41365C-page 219
To
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