PIC16F707-I/P Microchip Technology, PIC16F707-I/P Datasheet - Page 40
![IC MCU 8BIT FLASH 40-DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC16F707-I/P
Manufacturer Part Number
PIC16F707-I/P
Description
IC MCU 8BIT FLASH 40-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Specifications of PIC16F707-I/P
Core Size
8-Bit
Program Memory Size
14KB (8K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
36
Program Memory Type
FLASH
Ram Size
363 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 14x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC16F
No. Of I/o's
36
Ram Memory Size
363Byte
Cpu Speed
20MHz
No. Of Timers
6
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
I2C, SPI, AUSART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 14 Channel
On-chip Dac
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F707-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC16F707/PIC16LF707
4.1
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
• GIE bit of the INTCON register
• Interrupt enable bit(s) for the specific interrupt
• PEIE bit of the INTCON register (if the interrupt
The INTCON, PIR1 and PIR2 registers record individ-
ual interrupts via interrupt flag bits. Interrupt flag bits will
be set, regardless of the status of the GIE, PEIE and
individual Interrupt Enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
• PC is loaded with the interrupt vector 0004h
The ISR determines the source of the interrupt by
polling the interrupt flag bits. The interrupt flag bits must
be cleared before exiting the ISR to avoid repeated
FIGURE 4-2:
DS41418A-page 40
INSTRUCTION FLOW
event(s)
enable bit of the interrupt event is contained in the
PIE1 and PIE2 registers)
stack
GIE bit
(INTCON<7>)
INTF flag
(INTCON<1>)
CLKOUT
INT pin
OSC1
Note 1: INTF flag is sampled here (every Q1).
Instruction
Executed
Instruction
Fetched
PC
Operation
2: Asynchronous interrupt latency = 3-4 T
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 25.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
(3)
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
Q1
Inst (PC – 1)
Inst (PC)
(1)
INT PIN INTERRUPT TIMING
Q2
PC
(4)
Q3
Q4
(5)
Q1
Inst (PC + 1)
Inst (PC)
Q2
(1)
PC + 1
Q3
CY
Preliminary
. Synchronous latency = 3 T
Q4
Interrupt Latency
Q1
Dummy Cycle
Q2
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack and setting the GIE bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
4.2
Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is 3 instruction cycles. For asynchronous
interrupts, the latency is 3 to 4 instruction cycles,
depending on when the interrupt occurs. See Figure 4-2
for timing details.
PC + 1
—
Note 1: Individual interrupt flag bits are set,
Q3
2: All interrupts will be ignored while the GIE
Interrupt Latency
Q4
(2)
regardless of the state of any other
enable bits.
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
Q1
Dummy Cycle
CY
Inst (0004h)
, where T
Q2
0004h
Q3
2010 Microchip Technology Inc.
CY
Q4
= instruction cycle time.
Q1
Inst (0005h)
Q2
Inst (0004h)
0005h
Q3
Q4
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