PIC18F26K20-E/SO Microchip Technology, PIC18F26K20-E/SO Datasheet - Page 2

• Manufacturer Part Number: PIC18F26K20-E/SO
• Description: IC PIC MCU FLASH 16KX16 28-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26K20-E/SO

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: CCP/ECCP/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164303 - MODULE SKT FOR PM3 64TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F26K20/46K20
9. Module: MSSP SPI
10. Module: MSSP SPI
11. Module: MSSP SPI
12. Module: EUSART
13. Module: EUSART
DS80379A-page 2
In SPI Master mode, when the CKE bit is cleared
and the SMP bit is set, the last bit of the incoming
data stream (bit 0) at the SDI pin will not be
sampled properly.
Work around
None.
In SPI Master mode, when CKE bit is set, the
SSPBUF will reload the SSPSR output shift register
on every high-to-low transition of the SS pin.
Work around
Avoid using the SS pin when the CKE bit is set and
the MSSP is configured for SPI Master mode.
When SPI is enabled in Master mode with
CKE = 1 and CKP = 0, a 1/F
occur on the SCK pin.
Work around
Configure the SCK pin as an input until after the
MSSP is setup.
In Synchronous Master mode, when the SPBRG is
set to an odd number, the duty cycle of the CK
output will be skewed by one baud clock count.
Work around
High values of SPBRG will minimize the effect of
this anomaly.
In Synchronous Master mode, when the SPBRG is
set to 3 and the TXREG is written while the
previous character is still in the TX shift register, the
LS bit of the TXREG character may be corrupted
during transmission.
Work around
When SPBRG is set to 3, wait until the TRMT bit of
the TXSTA register is set before loading TXREG
with the next character to be transmitted.
OSC
wide pulse will
14. Module: EUSART
15. Module: System Clocks
16. Module: POR/BOR
17. Module: POR
18. Module: POR
In Synchronous Master mode, if the SPBRG
register is equal to 0, when the TXEN bit is set,
then writing to TXREG will properly start
transmission.
improperly out of phase with the data bits and the
clock will not stop at the end of the character
transmission.
Work around
Set SPBRG register to non-zero value before
setting the TXEN bit.
HFINTOSC output frequency is 16 MHz ± 3%,
25°C to 85°C.
Work around
None.
The POR rearm voltage may be below the low end
of the BOR range causing unexpected code
execution below the BOR range.
Work around
Use external power monitor to hold device in
Reset below 1.1 Volts.
The POR may release around 0.8 volts (below the
POR rearm voltage of 1.2V nominal) when V
rises from below either 0.60V when BOR is not
enabled, or 0.33V when BOR is enabled.
Work around
Use Power-up Timer when operating with the EC,
EXTRC or HFINTOSC oscillator modes. Ensure
that V
time.
The part may hang in the Reset state when V
falls to the POR rearm threshold of approximately
1.2 volts then rises at a rate faster than 7500 volts
per second to the operating range. Recovery from
the hung state is possible only by first lowering
V
raising V
Work around
Slow V
between the voltage supply and the V
bypassing should remain on the pin side of the
series resistor.
DD
to below the POR rearm threshold followed by
DD
DD
DD
rise time is less than the Power-up Timer
rise time by adding series resistance
to the operating range.
However,
© 2008 Microchip Technology Inc.
the
clock
DD
pin. V
will
DD
DD
DD
be