PIC16F628-20/SO Microchip Technology, PIC16F628-20/SO Datasheet - Page 104
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PIC16F628-20/SO
Manufacturer Part Number
PIC16F628-20/SO
Description
IC MCU FLASH 2KX14 COMP 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet
1.PIC16F627-04P.pdf
(170 pages)
Specifications of PIC16F628-20/SO
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
18-SOIC (7.5mm Width)
Controller Family/series
PIC16F
No. Of I/o's
16
Eeprom Memory Size
128Byte
Ram Memory Size
224Byte
Cpu Speed
20MHz
No. Of Timers
3
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
224 B
Interface Type
SCI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC164010 - MODULE SKT PROMATEII DIP/SOIC
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
PIC16F628-20/SOR
PIC16F628-20/SOR
PIC16F628-20/SOR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F628-20/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC16F62X
DS40300C-page 102
14.6.1
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION<6>) is set, or
falling, if INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
bit must be cleared in software in the interrupt service
routine before re-enabling this interrupt. The RB0/INT
interrupt can wake-up the processor from SLEEP, if the
INTE bit was set prior to going into SLEEP. The status
of the GIE bit decides whether or not the processor
branches to the interrupt vector following wake-up. See
Section 14.9 for details on SLEEP, and Figure 14-17
for timing of wake-up from SLEEP through RB0/INT
interrupt.
FIGURE 14-15:
Note 1: INTF flag is sampled here (every Q1).
OSC1
CLKOUT
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
PC
Instruction
Fetched
Instruction
Executed
INSTRUCTION FLOW
2: Asynchronous interrupt latency = 3-4 Tcy. Synchronous latency = 3 Tcy, where Tcy = instruction cycle time. Latency
3: CLKOUT is available in ER and INTRC Oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
on
(3)
RB0/INT INTERRUPT
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
the
Q1
Inst (PC-1)
RB0/INT
Inst (PC)
(1)
INT PIN INTERRUPT TIMING
Q2
PC
(4)
Q3
pin,
(5)
Q4
Q1
the
Inst (PC+1)
Inst (PC)
(1)
Q2
INTF
PC+1
Q3
Preliminary
bit
Q4
Interrupt Latency
Q1
Dummy Cycle
Q2
14.6.2
An overflow (FFh → 00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 6.0.
14.6.3
An input change on PORTB <7:4> sets the RBIF
(INTCON<0>) bit. The interrupt can be enabled/
disabled by setting/clearing the RBIE (INTCON<4>)
bit. For operation of PORTB (Section 5.2).
14.6.4
See Section 9.6 for complete description of comparator
interrupts.
PC+1
—
Note:
Q3
enabled/disabled
Q4
(2)
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
TMR0 INTERRUPT
PORTB INTERRUPT
COMPARATOR INTERRUPT
Q1
Dummy Cycle
Inst (0004h)
Q2
0004h
2003 Microchip Technology Inc.
Q3
by
Q4
setting/clearing
Q1
Inst (0005h)
Q2
Inst (0004h)
0005h
Q3
Q4
T0IE