PIC16F628-04/SS Microchip Technology, PIC16F628-04/SS Datasheet - Page 65

• Manufacturer Part Number: PIC16F628-04/SS
• Description: IC MCU FLASH 2KX14 COMP 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F628-04/SS

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Core Processor: PIC
• Speed: 4MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SSOP
• Controller Family/series: PIC16F
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 224Byte
• Cpu Speed: 4MHz
• No. Of Timers: 3
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 4 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 16
• Interface Type: SCI/USART
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOPAC164018 - MODULE SKT PROMATEII 20SSOP
• Data Converters: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

11.2.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
11.2.3
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
TABLE 11-3:
 2003 Microchip Technology Inc.
0Bh/8Bh/
10Bh/
18Bh
0Ch
8Ch
87h
0Eh
0Fh
10h
15h
16h
17h
Legend:
Address
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1.
INTCON
PIR1
PIE1
TRISB
TMR1L
TMR1H
T1CON
CCPR1L
CCPR1H
CCP1CON
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
Name
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
PORTB Data Direction Register
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1register
Capture/Compare/PWM register1 (LSB)
Capture/Compare/PWM register1 (MSB)
Bit 7
EEIE
EEIF
GIE
—
—
Bit 6
CMIF
CMIF
PEIE
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
CCP1X
Bit 5
RCIE
RCIF
T0IE
CCP1Y
Bit 4
INTE
TXIF
TXIE
Preliminary
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Bit 3
RBIE
—
—
11.2.4
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
CCP1IE TMR2IE
CCP1IF
Bit 2
T0IF
SPECIAL EVENT TRIGGER
TMR2IF
Bit 1
INTF
TMR1IF 0000 -000 0000 -000
TMR1IE 0000 -000 0000 -000
PIC16F62X
Bit 0
RBIF
0000 000x 0000 000u
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Value on
DS40300C-page 63
POR
Value on
RESETS
all other