PIC18F26K20-E/SP Microchip Technology, PIC18F26K20-E/SP Datasheet - Page 3
![IC PIC MCU FLASH 32KX16 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F26K20-E/SP
Manufacturer Part Number
PIC18F26K20-E/SP
Description
IC PIC MCU FLASH 32KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(456 pages)
3.PIC18F26K20-ISS.pdf
(6 pages)
4.PIC18F26K20-ISS.pdf
(10 pages)
5.PIC18F26K20-ISO.pdf
(430 pages)
Specifications of PIC18F26K20-E/SP
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
CCP, ECCP, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
19. Module: Clocks
20. Module: Comparators
21. Module: Comparators
22. Module: Data EEPROM Memory
23. Module: Program Flash Memory
© 2008 Microchip Technology Inc.
EC Mode operation is limited to a maximum of
48 MHz.
Work around
Use HS Clock mode for external clocking above
48 MHz.
Comparator input offset voltage is ± 25 mV and
may degrade over the lifetime of the part
accelerated by high temperature. The offset voltage
increases as the common-mode voltage decreases
with the following characteristics: Offset is ± 25 mV
when the common-mode voltage is V
is up to ± 50 mV when the common-mode voltage
is V
the common-mode voltage is 0V.
Work around
None.
When the CxON bit is clear, the output from the
comparator will be properly forced to zero, but the
CxPOL bit will improperly have no effect on the
CxOUT bit. This prevents presetting the compara-
tor change-on-interrupt mismatch latches as
described in the data sheet.
Work around
Configure one of the unused comparator input
channels as a digital output. Use that digital output
to manipulate the comparator output to the desired
CxOUT non-interrupt level. When the comparator
is then set to the desired inputs, the mismatch
latches will be preset to the non-interrupt level and
the CxIF flag can then be cleared.
The write/erase endurance of Data EE Memory is
limited to 10K cycles.
Work around
Use error correction method that stores data in
multiple locations.
The write/erase endurance of the PFM is limited to
1K cycles when V
degrades when V
Work around
For data tables in program Flash memory, use the
error correction method that stores data in multiple
locations.
DD
/2; The offset is greater than ± 50 mV when
DD
DD
is below 3V.
is above 3V. Endurance
DD
; The offset
24. Module: Input/Output (PIC18F26K20
25. Module: Timer 1
PIC18F26K20/46K20
Reading PORTE bit 3 always returns 0.
Work around
None.
In Asynchronous Counter mode, a false interrupt
may occur on the first rising T1CKI clock edge
after writing the TMR1H or TMR1L register.
Work around
Examine the TMR1H:TMR1L register pair in the
Interrupt
TMR1H:TMR1L register pair is less than the
preset value then service the interrupt. Otherwise,
disregard the interrupt and only clear the Timer1
interrupt flag.
only)
Service
Routine
DS80379A-page 3
(ISR).
If
the