PIC18LF24J50-I/ML Microchip Technology, PIC18LF24J50-I/ML Datasheet - Page 521
![IC PIC MCU FLASH 16K 2V 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18LF24J50-I/ML
Manufacturer Part Number
PIC18LF24J50-I/ML
Description
IC PIC MCU FLASH 16K 2V 28-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
Specifications of PIC18LF24J50-I/ML
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
16
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
16
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, MA180024, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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FIGURE 29-20:
TABLE 29-27: EUSARTx SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 29-21:
TABLE 29-28: EUSARTx SYNCHRONOUS RECEIVE REQUIREMENTS
© 2009 Microchip Technology Inc.
120
121
122
Param.
125
126
Param
No.
No.
Note:
RXx/DTx
TXx/CKx
Note:
T
T
T
RXx/DTx
TXx/CKx
T
T
CK
CKRF
Symbol
DTRF
CK
Symbol
DT
pin
pin
H2
L2
V2
Refer to Figure 29-4 for load conditions.
pin
pin
DT
DTL
CKL
V Sync XMIT (Master and Slave)
Refer to Figure 29-4 for load conditions.
Clock High to Data Out Valid
Clock Out Rise Time and Fall Time (Master mode)
Data Out Rise Time and Fall Time
Sync RCV (Master and Slave)
Data Hold before CKx ↓ (DTx hold time)
Data Hold after CKx ↓ (DTx hold time)
EUSARTx SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
EUSARTx SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
120
Characteristic
121
Characteristic
125
121
PIC18F46J50 FAMILY
126
Min
10
15
Min
Max
—
—
—
—
—
122
Units
Max
ns
ns
40
20
20
Units
ns
ns
ns
DS39931C-page 521
Conditions
Conditions
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