PIC16C716-20/P Microchip Technology, PIC16C716-20/P Datasheet - Page 19

• Manufacturer Part Number: PIC16C716-20/P
• Description: IC MCU OTP 2KX14 A/D PWM 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C716-20/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1059 - ADAPTER 18 ZIF BD W/18SO PLUGSDVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

2.2.2.5
This register contains the individual flag bits for the
peripheral interrupts.
FIGURE 2-8:
© 2005 Microchip Technology Inc.
bit7
bit 7:
bit 6:
bit 5-3: Unimplemented: Read as ‘0’
bit 2:
bit 1:
bit 0:
U-0
—
Unimplemented: Read as ‘0’
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode:
Unused in this mode
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
PIR1 Register
R/W-0
ADIF
PIR1 REGISTER (ADDRESS 0Ch)
U-0
—
U-0
—
R/W-0
—
CCP1IF
R/W-0
TMR2IF
R/W-0
Note:
TMR1IF
R/W-0
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
PIC16C712/716
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
-n = Value at POR Reset
read as ‘0’
DS41106B-page 17