PIC16F916-I/SO Microchip Technology, PIC16F916-I/SO Datasheet - Page 123
![IC PIC MCU FLASH 8KX14 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC16F916-I/SO
Manufacturer Part Number
PIC16F916-I/SO
Description
IC PIC MCU FLASH 8KX14 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F913-ISS.pdf
(330 pages)
3.PIC16F913-ISS.pdf
(8 pages)
4.PIC16F913-ISS.pdf
(34 pages)
5.PIC16F913-ISO.pdf
(274 pages)
Specifications of PIC16F916-I/SO
Program Memory Type
FLASH
Program Memory Size
14KB (8K x 14)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
352 B
Interface Type
SSP/I2C/AUSART/SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120
Minimum Operating Temperature
- 40 C
On-chip Adc
5-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F916-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F913-ISS PDF datasheet #2
- PIC16F913-ISS PDF datasheet #3
- PIC16F913-ISS PDF datasheet #4
- PIC16F913-ISO PDF datasheet #5
- Current page: 123 of 274
- Download datasheet (5Mb)
9.8
The LCD timing generation provides an interrupt that
defines the LCD frame timing. This interrupt can be
used to coordinate the writing of the pixel data with the
start of a new frame. Writing pixel data at the frame
boundary allows a visually crisp transition of the image.
This interrupt can also be used to synchronize external
events to the LCD.
A new frame is defined to begin at the leading edge of
the COM0 common signal. The interrupt will be set
immediately after the LCD controller completes
accessing all pixel data required for a frame. This will
occur at a fixed interval before the frame boundary
(T
will begin to access data for the next frame within the
interval from the interrupt to when the controller begins
to access data after the interrupt (T
must be written within T
controller will begin to access the data for the next
frame.
FIGURE 9-16:
2004 Microchip Technology Inc.
FINT
), as shown in Figure 9-16. The LCD controller
COM0
COM1
COM2
COM3
T
T
FWR
FINT
LCD Interrupts
= T
= (T
(T
FRAME
FWR
FWR
/2 – (2 T
/2 – (1 T
Frame
Boundary
/2*(LMUX<1:0> + 1) + T
(EXAMPLE – TYPE-B, NON-STATIC)
WAVEFORMS AND INTERRUPT TIMING IN QUARTER-DUTY CYCLE DRIVE
FWR
CY
CY
, as this is when the LCD
+ 40 ns))
+ 40 ns))
FWR
minimum = 1.5(T
maximum = 1.5(T
). New data
CY
/2
Preliminary
2 Frames
FRAME
FRAME
Frame
Boundary
/4) – (2 T
/4) – (1 T
When the LCD driver is running with Type-B waveforms
and the LMUX<1:0> bits are not equal to ‘00’, there are
some additional issues that must be addressed. Since
the DC voltage on the pixel takes two frames to maintain
zero volts, the pixel data must not change between
subsequent frames. If the pixel data were allowed to
change, the waveform for the odd frames would not
necessarily be the complement of the waveform
generated in the even frames and a DC component
would be introduced into the panel. Therefore, when
using Type-B waveforms, the user must synchronize the
LCD pixel updates to occur within a subframe after the
frame interrupt.
To correctly sequence writing while in Type-B, the
interrupt will only occur on complete phase intervals. If the
user attempts to write when the write is disabled, the
WERR (LCDCON<5>) bit is set.
Note:
CY
CY
LCD
Interrupt
Occurs
+ 40 ns)
+ 40 ns)
The interrupt is not generated when the
Type-A waveform is selected and when the
Type-B with no multiplex (static) is
selected.
T
FWR
T
FINT
PIC16F91X
Controller Accesses
Next Frame Data
Frame
Boundary
DS41250B-page 121
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
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