PIC18F26J11-I/SO Microchip Technology, PIC18F26J11-I/SO Datasheet - Page 21
![IC PIC MCU FLASH 64K 2V 28-SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18F26J11-I/SO
Manufacturer Part Number
PIC18F26J11-I/SO
Description
IC PIC MCU FLASH 64K 2V 28-SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
4.PIC18F26J11-ISO.pdf
(28 pages)
Specifications of PIC18F26J11-I/SO
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, MA180023, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
TABLE 5-5:
© 2008 Microchip Technology Inc.
DSWTPS3:DSWTPS0
DSWDTEN
DSBOREN
RTCOSC
DSWDTOSC
MSSPMSK
IOL1WAY
WPCFG
WPEND
Note 1: The Configuration bits can only be programmed indirectly by programming the Flash Configuration Word.
Bit Name
(4)
2: The Configuration bits are reset to ‘1’ only on V
3: These bits are not implemented in PIC18F46J11 family devices.
4: Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code
5: The WPFP write protection does not override CPn. Write-protect is an OR function of the two.
(1,2)
protection, perform an ICSP™ Bulk Erase operation.
PIC18F46J11 AND PIC18F46J50 FAMILY DEVICES: BIT DESCRIPTIONS (CONTINUED)
Configuration
CONFIG3H
CONFIG3H
CONFIG3L
CONFIG3L
CONFIG3L
CONFIG3L
CONFIG3L
CONFIG4L
CONFIG4L
Words
Deep Sleep Watchdog Timer Postscale Select bits
The DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms.
1111 = 1:2,147,483,648 (25.7 days)
1110 = 1:536,870,912 (6.4 days)
1101 = 1:134,217,728 (38.5 hours)
1100 = 1:33,554,432 (9.6 hours)
1011 = 1:8,388,608 (2.4 hours)
1010 = 1:2,097,152 (36 minutes)
1001 = 1:524,288 (9 minutes)
1000 = 1:131,072 (135 seconds)
0111 = 1:32,768 (34 seconds)
0110 = 1:8,192 (8.5 seconds)
0101 = 1:2,048 (2.1 seconds)
0100 = 1:512 (528 ms)
0011 = 1:128 (132 ms)
0010 = 1:32 (33 ms)
0001 = 1:8 (8.3 ms)
0000 = 1:2 (2.1 ms)
Deep Sleep Watchdog Timer Enable bit
1 = DSWDT enabled
0 = DSWDT disabled
1 = BOR enabled in Deep Sleep
0 = BOR disabled in Deep Sleep (does not affect operation in non Deep Sleep modes)
RTCC Reference Clock Select bit
1 = RTCC uses T1OSC/T1CKI as reference clock
0 = RTCC uses INTOSC/INTRC as reference clock
DSWDT Reference Clock Select bit
1 = DSWDT uses INTOSC/INTRC as reference clock
0 = DSWDT uses T1OSC/T1CKI as reference clock
MSSP 7-Bit Address Masking Mode Enable bit
1 = 7-Bit Address Masking mode enable
0 = 5-Bit Address Masking mode enable
IOLOCK Bit One-Way Set Enable bit
1 = The IOLOCK bit (PPSCON<0>) can be set once, provided the unlock sequence has
0 = The IOLOCK bit (PPSCON<0>) can be set and cleared as needed, provided the
Write/Erase Protect Configuration Words Page bit (valid when WPDIS = 0)
1 = Configuration Words page is not erase/write-protected, regardless of WPEND and
0 = Configuration Words page is erase/write-protected, regardless of WPEND and
1 = Flash pages, WPFP<5:0> to Configuration Words page, are write/erase-protected
0 = Flash pages, 0 to WPFP<5:0> are write/erase-protected
Deep Sleep BOR Enable bit
Write/Erase Protect Region Select bit (valid when WPDIS = 0)
PIC18F2XJXX/4XJXX FAMILY
been completed. Once set, the Peripheral Pin Select registers cannot be written to a
second time.
unlock sequence has been completed
WPFP<5:0> settings
WPFP<5:0> settings
DD
Reset; it is reloaded with the programmed value at any device Reset.
Description
DS39687D-page 21