PIC18LF44J50-I/PT Microchip Technology, PIC18LF44J50-I/PT Datasheet - Page 36
![IC PIC MCU FLASH 16K 2V 44-TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18LF44J50-I/PT
Manufacturer Part Number
PIC18LF44J50-I/PT
Description
IC PIC MCU FLASH 16K 2V 44-TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
Specifications of PIC18LF44J50-I/PT
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
22
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180024
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF44J50-I/PT
Manufacturer:
Microchip Technology
Quantity:
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capacitors are also connected from each pin to ground.
PIC18F46J50 FAMILY
2.4
The 8 MHz INTOSC included in all PIC18F46J50 Fam-
ily devices is extremely accurate. When the 8 MHz
INTOSC is used with the 96 MHz PLL, it may be used
to derive the USB module clock. The high accuracy of
the INTOSC will allow the application to meet
low-speed USB signal rate specifications.
2.5
Like
PIC18F46J50 Family includes a feature that allows the
device clock source to be switched from the main
oscillator to an alternate, low-frequency clock source.
PIC18F46J50 Family devices offer two alternate clock
sources. When an alternate clock source is enabled,
the various power-managed operating modes are
available.
Essentially, there are three clock sources for these
devices:
• Primary Oscillators
• Secondary Oscillators
• Internal Oscillator Block
The Primary Oscillators include the External Crystal
and Resonator modes, the External Clock modes and
the internal oscillator block. The particular mode is
defined by the FOSC<2:0> Configuration bits. The
details of these modes are covered earlier in this
chapter.
The Secondary Oscillators are external sources that
are not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power-managed mode.
PIC18F46J50 Family devices offer the Timer1 oscillator
as a secondary oscillator. This oscillator, in all
power-managed modes, is often the time base for
functions such as a Real-Time Clock (RTC). Most often,
a 32.768 kHz watch crystal is connected between the
RC0/T1OSO/T1CKI/RP11 and RC1/T1OSI/UOE/RP12
pins. Like the HS Oscillator mode circuits, loading
The Timer1 oscillator is discussed in larger detail in
Section 12.5 “Timer1 Oscillator”.
In addition to being a primary clock source, the
postscaled
power-managed mode clock source. The INTRC
source is also used as the clock source for several
special features, such as the WDT and Fail-Safe Clock
Monitor (FSCM).
DS39931C-page 36
previous
USB From INTOSC
Clock Sources and Oscillator
Switching
internal
PIC18
clock
enhanced
is
available
devices,
as
the
a
2.5.1
The OSCCON register (Register 2-2) controls several
aspects of the device clock’s operation, both in
full-power operation and in power-managed modes.
The System Clock Select bits, SCS<1:0>, select the
clock source. The available clock sources are the
primary clock (defined by the FOSC<2:0> Configura-
tion bits), the secondary clock (Timer1 oscillator) and
the postscaled internal clock.The clock source changes
immediately, after one or more of the bits is written to,
following a brief clock transition interval. The SCS bits
are cleared on all forms of Reset.
The
IRCF<2:0>, select the frequency output provided on
the postscaled internal clock line. The choices are the
INTRC source, the INTOSC source (8 MHz) or one of
the frequencies derived from the INTOSC postscaler
(31 kHz to 4 MHz). If the postscaled internal clock is
supplying the device clock, changing the states of
these bits will have an immediate change on the inter-
nal oscillator’s output. On device Resets, the default
output frequency of the INTOSC postscaler is set at
4 MHz.
When an output frequency of 31 kHz is selected
(IRCF<2:0> = 000), users may choose the internal
oscillator, which acts as the source. This is done with
the
(OSCTUNE<7>). Setting this bit selects INTOSC as a
31.25 kHz clock source by enabling the divide-by-256
output of the INTOSC postscaler. Clearing INTSRC
selects INTRC (nominally 31 kHz) as the clock source.
This option allows users to select the tunable and more
precise INTOSC as a clock source, while maintaining
power savings with a very low clock speed. Regardless
of the setting of INTSRC, INTRC always remains the
clock source for features such as the WDT and the
FSCM.
The OSTS and T1RUN bits indicate which clock source
is currently providing the device clock. The OSTS bit
indicates that the Oscillator Start-up Timer (OST) has
timed out and the primary clock is providing the device
clock in primary clock modes. The T1RUN bit
(T1CON<6>) indicates when the Timer1 oscillator is
providing the device clock in secondary clock modes.
In power-managed modes, only one of these bits will
be set at any time. If none of these bits are set, the
INTRC is providing the clock or the internal oscillator
block has just started and is not yet stable.
The IDLEN bit determines if the device goes into Sleep
mode, or one of the Idle modes, when the SLEEP
instruction is executed.
INTSRC
Internal
OSCILLATOR CONTROL REGISTER
Oscillator
bit
in
© 2009 Microchip Technology Inc.
the
Frequency
OSCTUNE
Select
register
bits,
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