PIC16F87-I/SO Microchip Technology, PIC16F87-I/SO Datasheet - Page 146
![IC MCU FLASH 4KX14 EEPROM 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16F87-I/SO
Manufacturer Part Number
PIC16F87-I/SO
Description
IC MCU FLASH 4KX14 EEPROM 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F87-IP.pdf
(228 pages)
5.PIC16F87-IP.pdf
(8 pages)
6.PIC16F87-IP.pdf
(4 pages)
7.PIC16F87-IP.pdf
(8 pages)
8.PIC16F87-IP.pdf
(24 pages)
9.PIC16F88-ISO.pdf
(214 pages)
Specifications of PIC16F87-I/SO
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
18-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
SSP/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA12XP080 - ADAPTER DEVICE FOR MPLAB-ICE
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F87-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC16F87/88
15.12.4
The Fail-Safe Clock Monitor (FSCM) is designed to
allow the device to continue to operate even in the
event of an oscillator failure.
FIGURE 15-10:
The FSCM function is enabled by setting the FCMEN
bit in Configuration Word 2.
In the event of an oscillator failure, the FSCM will gen-
erate an oscillator fail interrupt and will switch the sys-
tem clock over to the internal oscillator. The system
will continue to come from the internal oscillator until
the fail-safe condition is exited. The fail-safe condition
is exited with either a RESET, the execution of a
SLEEP instruction or a write to the OSCCON register.
The frequency of the internal oscillator will depend
upon the value contained in the IRCF bits. Another
clock source can be selected via the IRCF and the
SCS bits of the OSCCON register.
FIGURE 15-11:
DS30487B-page 144
31.25 kHz
Peripheral
Oscillator
(32 s)
INTRC
Clock
Sample Clock
Note:
CM Output
OSCFIF
System
FAIL-SAFE OPTION
Output
Clock
(2.048 ms)
(Q)
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
488 Hz
÷ 64
FSCM BLOCK DIAGRAM
FSCM TIMING DIAGRAM
(edge-triggered)
Clock Monitor
Latch (CM)
C
S
CM Test
Q
Q
Detected
Failure
Clock
Preliminary
The FSCM sample clock is generated by dividing the
INTRC clock by 64. This will allow enough time
between FSCM sample clocks for a system clock edge
to occur.
On the rising edge of the postscaled clock, the moni-
toring latch (CM = 0) will be cleared. On a falling edge
of the primary or secondary system clock, the monitor-
ing latch will be set (CM = 1). In the event that a falling
edge of the postscaled clock occurs, and the
monitoring latch is not set, a clock failure has been
detected.
While in Fail-Safe mode, a RESET will exit the fail-
safe condition. If the primary clock source is config-
ured for a crystal, the OST timer will wait for the 1024
clock cycles for the OST time-out, and the device will
continue running from the internal oscillator until the
OST is complete. A SLEEP instruction, or a write to the
SCS bits (where SCS bits do not = 00), can be
performed to put the device into a low-power mode.
If RESET occurs while in Fail-Safe mode and the pri-
mary clock source is EC, or RC, then the device will
immediately switch back to EC or RC mode.
15.12.4.1
A write to the OSCCON register, or SLEEP instruction
will end the fail-safe condition. The system clock will
default to the source selected by the SCS bits, which
is either T1OSC, INTRC, or none (SLEEP mode).
However, the FSCM will continue to monitor the sys-
tem clock. If the secondary clock fails, the device will
immediately switch to the internal oscillator clock. If
OSFIE is set, an interrupt will be generated.
CM Test
Note:
Oscillator
Failure
Two-Speed Start-up mode is automatically
enabled when the fail-safe option is
enabled.
Fail-Safe in Low-power Mode
2003 Microchip Technology Inc.
Detected
Failure
CM Test