PIC18F66J15-I/PT Microchip Technology, PIC18F66J15-I/PT Datasheet - Page 145

• Manufacturer Part Number: PIC18F66J15-I/PT
• Description: IC PIC MCU FLASH 48KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F66J15-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 96KB (48K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 11-15: PORTG FUNCTIONS
TABLE 11-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
© 2009 Microchip Technology Inc.
RG0/ECCP3/
P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/
P3D
RG4/CCP5/
P1D
Legend:
PORTG
LATG
TRISG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1:
Pin Name
Name
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Unimplemented on 64-pin devices, read as ‘0’.
Function
ECCP3
CCP4
CCP5
RG0
RG2
RG3
RG4
P3A
R21
TX2
CK2
RX2
DT2
P3D
P1D
RDPU
Bit 7
—
—
Setting
TRIS
0
1
0
0
1
1
1
1
0
1
1
1
1
0
1
0
1
0
0
1
0
1
0
REPU
Bit 6
—
—
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
RJPU
Bit 5
—
—
Type
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
(1)
TRISG4
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Synchronous serial data output (EUSART2 module); takes priority over
port data.
Synchronous serial data input (EUSART2 module). User must configure
as an input.
LATG<2> data output.
PORTG<2> data input.
Asynchronous serial receive data input (EUSART2 module).
Synchronous serial data output (EUSART2 module); takes priority over
port data.
Synchronous serial data input (EUSART2 module). User must configure
as an input.
LATG<3> data output.
PORTG<3> data input.
CCP4 compare output and CCP4 PWM output; takes priority over port data.
CCP4 capture input.
ECCP3 Enhanced PWM output, Channel D; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATG<4> data output.
PORTG<4> data input.
CCP5 compare output and CCP5 PWM output; takes priority over port data.
CCP5 capture input.
ECCP1 Enhanced PWM output, Channel D; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATG<0> data output.
PORTG<0> data input.
CCP3 compare and PWM output; takes priority over port data.
CCP3 capture input.
ECCP3 Enhanced PWM output, Channel A; takes priority over port and
LATG<1> data output.
PORTG<1> data input.
Synchronous serial clock input (EUSART2 module).
LATG4
Bit 4
RG4
PIC18F87J10 FAMILY
TRISG3
LATG3
Bit 3
RG3
TRISG2
LATG2
Bit 2
RG2
Description
TRISG1
LATG1
Bit 1
RG1
TRISG0
LATG0
Bit 0
RG0
DS39663F-page 143
Values on
Reset
page
56
56
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