PIC18LF44J50-I/ML Microchip Technology, PIC18LF44J50-I/ML Datasheet - Page 420
![IC PIC MCU FLASH 16K 2V 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18LF44J50-I/ML
Manufacturer Part Number
PIC18LF44J50-I/ML
Description
IC PIC MCU FLASH 16K 2V 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
Specifications of PIC18LF44J50-I/ML
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
22
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180024
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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- Download datasheet (9Mb)
PIC18F46J50 FAMILY
REGISTER 26-6:
REGISTER 26-7:
DS39931C-page 420
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-4
bit 3
bit 2-1
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-0
Note 1:
WPCFG
R/WO-1
U-1
—
The “Configuration Words page” contains the FCWs and is the last page of implemented Flash memory on
a given device. Each page consists of 1,024 bytes. For example, on a device with 64 Kbytes of Flash, the
first page is 0 and the last page (Configuration Words page) is 63 (3Fh).
Unimplemented: Program the corresponding Flash Configuration bit to ‘1’
MSSPMSK: MSSP 7-Bit Address Masking Mode Enable bit
1 = 7-Bit Address Masking mode enabled
0 = 5-Bit Address Masking mode enabled
Unimplemented: Read as ‘0’
IOL1WAY: IOLOCK One-Way Set Enable bit
1 = IOLOCK bit (PPSCON<0>) can be set once, provided the unlock sequence has been completed.
0 = IOLOCK bit (PPSCON<0>) can be set and cleared as needed, provided the unlock sequence has
WPCFG: Write/Erase Protect Configuration Region Select bit (valid when WPDIS = 0)
1 = Configuration Words page is not erase/write-protected unless WPEND and WPFP<5:0> settings
0 = Configuration Words page is erase/write-protected, regardless of WPEND and WPFP<5:0>
WPEND: Write/Erase Protect Region Select bit (valid when WPDIS = 0)
1 = Flash pages WPFP<5:0> to (Configuration Words page) are write/erase protected
0 = Flash pages 0 to WPFP<5:0> are erase/write-protected
WPFP<5:0>: Write/Erase Protect Page Start/End Location bits
Used with WPEND bit to define which pages in Flash will be write/erase protected.
WPEND
R/WO-1
Once set, the Peripheral Pin Select registers cannot be written to a second time.
been completed
include the Configuration Words page
U-1
—
CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
WO = Write-Once bit
WO = Write-Once bit
‘1’ = Bit is set
‘1’ = Bit is set
R/WO-1
WPFP5
U-1
—
R/WO-1
WPFP4
U-1
—
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
MSSPMSK
R/WO-1
R/WO-1
WPFP3
R/WO-1
WPFP2
U-0
—
© 2009 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
R/WO-1
WPFP1
U-0
—
IOL1WAY
R/WO-1
R/WO-1
WPFP0
(1)
bit 0
bit 0
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