PIC16F872-I/SO Microchip Technology, PIC16F872-I/SO Datasheet - Page 55

• Manufacturer Part Number: PIC16F872-I/SO
• Description: IC MCU FLASH 2KX14 EE 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F872-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Eeprom Size: 64 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C/SPI/SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 10-bit
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 20 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL309-1073 - ADAPTER 28-SOIC TO 28-SOIC309-1024 - ADAPTER 28-SOIC TO 28-DIP309-1023 - ADAPTER 28-SOIC TO 28-DIP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 9-2:
2002 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3-0
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS: 14h)
bit 7
WCOL: Write Collision Detect bit
Master mode:
1 = A write to SSPBUF was attempted while the I
0 = No collision
Slave mode:
1 = SSPBUF register is written while still transmitting the previous word (must be cleared in software)
0 = No collision
In SPI mode:
1 = A new byte is received while SSPBUF holds previous data. Data in SSPSR is lost on overflow.
0 = No overflow
In I
1 = A byte is received while the SSPBUF is holding the previous byte. SSPOV is a "don’t care" in
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
In SPI mode:
When enabled, these pins must be properly configured as input or output.
1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I
When enabled, these pins must be properly configured as input or output.
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
In SPI mode:
1 = IDLE state for clock is a high level
0 = IDLE state for clock is a low level
In I
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I
Unused in this mode
0000 = SPI Master mode, clock = F
0001 = SPI Master mode, clock = F
0010 = SPI Master mode, clock = F
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110 = I
0111 = I
1000 = I
1011 = I
1110 = I
1111 = I
1001, 1010, 1100, 1101 = reserved
Legend:
R = Readable bit
- n = Value at POR
SSPOV: Receive Overflow Indicator bit
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
WCOL
R/W-0
2
2
2
2
In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid over-
flows. In Master mode, the overflow bit is not set since each operation is initiated by writing to
the SSPBUF register. (Must be cleared in software.)
Transmit mode. (Must be cleared in software.)
C mode:
C mode:
C slave mode:
C master mode:
enabled
enabled
2
2
2
2
2
2
C Slave mode, 7-bit address
C Slave mode, 10-bit address
C Master mode, clock = F
C Firmware Controlled Master mode (slave idle)
C Firmware Controlled Master mode, 7-bit address with START and STOP bit interrupts
C Firmware Controlled Master mode, 10-bit address with START and STOP bit interrupts
SSPOV
R/W-0
W = Writable bit
’1’ = Bit is set
SSPEN
R/W-0
OSC
OSC
OSC
OSC
/4
/16
/64
R/W-0
/ (4 * (SSPADD+1)
CKP
2
C conditions were not valid
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
SSPM3
R/W-0
SSPM2
R/W-0
PIC16F872
x = Bit is unknown
SSPM1
R/W-0
DS30221B-page 53
SSPM0
R/W-0
bit 0