PIC18F67J10-I/PT Microchip Technology, PIC18F67J10-I/PT Datasheet - Page 207
![IC PIC MCU FLASH 64KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F67J10-I/PT
Manufacturer Part Number
PIC18F67J10-I/PT
Description
IC PIC MCU FLASH 64KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F63J11-IPT.pdf
(36 pages)
3.PIC18F85J10-IPT.pdf
(410 pages)
4.PIC18F85J10-IPT.pdf
(10 pages)
5.PIC18F85J10-IPT.pdf
(10 pages)
6.PIC18F85J10-IPT.pdf
(8 pages)
7.PIC18F66J15-IPT.pdf
(400 pages)
Specifications of PIC18F67J10-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
SPI/I2C/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
50
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
A/d Bit Size
10 bit
A/d Channels Available
11
Height
1 mm
Length
10 mm
Supply Voltage (max)
2.7 V, 3.6 V
Supply Voltage (min)
2 V, 2.7 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67J10-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F67J10-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F63J11-IPT PDF datasheet #2
- PIC18F85J10-IPT PDF datasheet #3
- PIC18F85J10-IPT PDF datasheet #4
- PIC18F85J10-IPT PDF datasheet #5
- PIC18F85J10-IPT PDF datasheet #6
- PIC18F66J15-IPT PDF datasheet #7
- Current page: 207 of 400
- Download datasheet (7Mb)
18.4.3.2
Masking an address bit causes that bit to become a
“don’t care”. When one address bit is masked, two
addresses will be Acknowledged and cause an
interrupt. It is possible to mask more than one address
bit at a time, which makes it possible to Acknowledge
up to 31 addresses in 7-bit mode and up to
63 addresses in 10-bit mode (see Example 18-2).
The I
masking is used or not. However, when address
masking is used, the I
multiple addresses and cause interrupts. When this
occurs, it is necessary to determine which address
caused the interrupt by checking SSPxBUF.
• 7-bit Address mode
EXAMPLE 18-2:
© 2006 Microchip Technology Inc.
Address Mask bits, ADMSK<5:1>, mask the
corresponding address bits in the SSPxADD
register. For any ADMSK bits that are active
(ADMSK<n> = 1), the corresponding address bit
is ignored (ADD<n> = x). For the module to issue
an address Acknowledge, it is sufficient to match
only on addresses that do not have an active
address mask.
2
C slave behaves the same way whether address
7-bit Addressing:
10-bit Addressing:
SSPxADD<7:1> = 1010 0000
ADMSK<5:1>
Addresses Acknowledged = 0xA0, 0xA2, 0xA4, 0xA6
SSPxADD<7:0> = 1010 0000 (The two MSbs are ignored in this example since they are not affected.)
ADMSK<5:1>
Addresses Acknowledged = 0xA0, 0xA1, 0xA2, 0xA3
The upper two bits are not affected by the address masking.
Address Masking
ADDRESS MASKING
2
C slave can Acknowledge
= 00 111
= 00 111
0xA8, 0xAA, 0xAC, 0xAE
0xA4, 0xA5, 0xA6, 0xA7
0xA8, 0xA9, 0xAA 0xAB
0xAC, 0xAD, 0xAE, 0xAF
Preliminary
• 10-bit Address mode
Address Mask bits, ADMSK<5:2>, mask the
corresponding address bits in the SSPxADD
register. In addition, ADMSK<1> simultaneously
masks the two LSBs of the address, ADD<1:0>.
For
(ADMSK<n> = 1), the corresponding address bit
is ignored (ADD<n> = x). Also note, that although
in 10-bit Addressing mode, the upper address bits
reuse part of the SSPxADD register bits, the
address mask bits do not interact with those bits.
They only affect the lower address bits.
Note 1: ADMSK<1>
any
2: The two Most Significant bits of the
Significant bits of the address.
address are not affected by address
masking.
ADMSK
PIC18F87J10
bits
masks
that
DS39663D-page 205
the
are
two
active
Least
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