PIC18LF1320-I/SS Microchip Technology, PIC18LF1320-I/SS Datasheet - Page 166
![IC MCU FLASH 4KX16 EEPROM 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC18LF1320-I/SS
Manufacturer Part Number
PIC18LF1320-I/SS
Description
IC MCU FLASH 4KX16 EEPROM 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F1220-ISO.pdf
(308 pages)
3.PIC18F1220-ISO.pdf
(8 pages)
4.PIC18F1220-ISO.pdf
(6 pages)
5.PIC18F1220-ISO.pdf
(10 pages)
6.PIC18F1220-ISO.pdf
(4 pages)
7.PIC18F1220-EP.pdf
(310 pages)
Specifications of PIC18LF1320-I/SS
Program Memory Type
FLASH
Program Memory Size
8KB (4K x 16)
Package / Case
20-SSOP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
7-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF1320-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F1220-ISO PDF datasheet #2
- PIC18F1220-ISO PDF datasheet #3
- PIC18F1220-ISO PDF datasheet #4
- PIC18F1220-ISO PDF datasheet #5
- PIC18F1220-ISO PDF datasheet #6
- PIC18F1220-EP PDF datasheet #7
- Current page: 166 of 310
- Download datasheet (6Mb)
PIC18F1220/1320
17.8
An A/D conversion can be started by the “special event
trigger” of the CCP1 module. This requires that the
CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to auto-
matically repeat the A/D acquisition period with minimal
TABLE 17-2:
DS39605C-page 164
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PORTA
TRISA
PORTB
TRISB
LATB
Legend:
Note 1:
Name
2:
3:
Use of the CCP1 Trigger
Read PORTB pins, Write LATB Latch
PORTB Data Direction Register
PORTB Output Data Latch
TRISA7
A/D Result Register High Byte
A/D Result Register Low Byte
x = unknown, u = unchanged, q = depends on CONFIG1H<3:0>, – = unimplemented, read as ‘0’.
Shaded cells are not used for A/D conversion.
RA5 port bit is available only as an input pin when the MCLRE bit in the configuration register is ‘0’.
RA6 and TRISA6 are available only when the primary oscillator mode selection offers RA6 as a port pin; otherwise, RA6
always reads ‘0’, TRISA6 always reads ‘1’ and writes to both are ignored (see CONFIG1H<3:0>).
RA7 and TRISA7 are available only when the internal RC oscillator is configured as the primary oscillator in
CONFIG1H<3:0>; otherwise, RA7 always reads ‘0’, TRISA7 always reads ‘1’ and writes to both are ignored.
OSCFIF
OSCFIE
OSCFIP
VCFG1
RA7
ADFM
GIEH
Bit 7
GIE/
—
—
—
—
(3)
(3)
SUMMARY OF A/D REGISTERS
TRISA6
VCFG0
PCFG6
RA6
PEIE/
GIEL
ADIF
ADIE
ADIP
Bit 6
—
—
—
—
(2)
(2)
TMR0IE
PCFG5
ACQT2
RA5
RCIF
RCIE
RCIP
Bit 5
—
—
—
—
—
(1)
PORTA Data Direction Register
ACQT1
PCFG4
INT0IE
CHS2
EEIE
EEIP
Bit 4
TXIF
TXIE
TXIP
EEIF
RA4
PCFG3
ACQT0
CHS1
RBIE
Bit 3
RA3
—
—
—
—
—
—
TMR0IF
CCP1IF
CCP1IE
CCP1IP
PCFG2
ADCS2
LVDIE
LVDIP
LVDIF
CHS0
software overhead (moving ADRESH/ADRESL to the
desired location). The appropriate analog input
channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
T
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D
module, but will still reset the Timer1 (or Timer3)
counter.
Bit 2
RA2
ACQ
time selected before the “special event trigger”
GO/DONE
TMR2IE
TMR2IP
TMR3IE
TMR3IP
TMR2IF
TMR3IF
PCFG1
ADCS1
INT0IF
Bit 1
RA1
TMR1IF
TMR1IE
TMR1IP
PCFG0
ADCS0
ADON
RBIF
Bit 0
RA0
—
—
—
2004 Microchip Technology Inc.
0000 0000
-000 -000
-000 -000
-111 -111
0--0 -00-
0--0 -00-
1--1 -11-
xxxx xxxx
xxxx xxxx
00-0 0000
-000 0000
0-00 0000
qq0x 0000
qq-1 1111
xxxx xxxx
1111 1111
xxxx xxxx
POR, BOR
Value on
0000 0000
-000 -000
-000 -000
-111 -111
0--0 -00-
0--0 -00-
1--1 -11-
uuuu uuuu
uuuu uuuu
00-0 0000
-000 0000
0-00 0000
uu0u 0000
11-1 1111
uuuu uuuu
1111 1111
uuuu uuuu
Value on
all other
Resets
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